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Architectural Synthesis with Interconnection Cost Control

Christophe Jégo, Emmanuel Casseau, Eric Martin. Architectural Synthesis with Interconnection Cost Control. In L. Miguel Silveira, Srinivas Devadas, Ricardo Augusto da Luz Reis, editors, VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI 99), December 1-4, 1999, Lisbon, Portugal. Volume 162 of IFIP Conference Proceedings, pages 509-520, Kluwer, 1999.

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