Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto. 256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. In 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011. pages 524-527, IEEE, 2011. [doi]
Abstract is missing.