Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley. BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010. pages 849-854, IEEE, 2010. [doi]
Abstract is missing.