A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl

Marcin Rogawski, Kris Gaj, Ekawat Homsirikamol. A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl. Microprocessors and Microsystems, 37(6-7):572-582, 2013. [doi]

Abstract

Abstract is missing.