A hybrid SDC/SDF architecture for area and power minimization of floating-point FFT computations - researchr publication

researchr

You are not signed in
Sign in
Sign up

Mingyu Wang, Zhaolin Li. A hybrid SDC/SDF architecture for area and power minimization of floating-point FFT computations. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 2170-2173, IEEE, 2016. [doi]

Abstract is missing.

runs on WebDSL