A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology - researchr publication

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Chua-Chin Wang, Wen-Je Lu, Hsin-Yuan Tseng. A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013. pages 2079-2082, IEEE, 2013. [doi]

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