An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs

Paolo Zicari, Pasquale Corsonello, Stefania Perri. An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs. In 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006. pages 168-171, IEEE, 2006. [doi]

Abstract

Abstract is missing.