Abstract is missing.
- Processor Architecture for Trustworthy ComputersRuby B. Lee. 1-2 [doi]
- Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded SystemsAmjad Mohsen, Richard Hofmann. 3-14 [doi]
- Energy-Effective Instruction Fetch Unit for Wide Issue ProcessorsJuan L. Aragón, Alexander V. Veidenbaum. 15-27 [doi]
- Rule-Based Power-Balanced VLIW Instruction Scheduling with UncertaintyShu Xiao, Edmund Ming-Kit Lai, A. Benjamin Premkumar. 28-40 [doi]
- An Innovative Instruction Cache for Embedded ProcessorsCheol Kim, Sung Chung, Chu Shik Jhon. 41-51 [doi]
- Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) ProcessorDavid Fitrio, Jugdutt Singh, Aleksandar Stojcevski. 52-64 [doi]
- Design of an Efficient Multiplier-Less Architecture for Multi-dimensional ConvolutionMing Z. Zhang, Hau T. Ngo, Vijayan K. Asari. 65-78 [doi]
- A Pipelined Hardware Architecture for Motion Estimation of H.264/AVCSu-Jin Lee, Cheong-Ghil Kim, Shin-Dug Kim. 79-89 [doi]
- Embedded Intelligent Imaging On-Board Small SatellitesSiti Yuhaniz, Tanya Vladimirova, Martin Sweeting. 90-103 [doi]
- Architectural Enhancements for Color Image and Video Processing on Embedded SystemsJongmyon Kim, D. Scott Wills, Linda M. Wills. 104-117 [doi]
- A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and OutputYufeng Zhang, Yi Zhou, Jianhua Chen, Xinling Shi, Zhenyu Guo. 118-130 [doi]
- A Power-Efficient Processor Core for Reactive Embedded ApplicationsLei Yang, Morteza Biglari-Abhari, Zoran A. Salcic. 131-142 [doi]
- A Stream Architecture Supporting Multiple Stream Execution ModelsNan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang. 143-156 [doi]
- The Challenges of Massive On-Chip ConcurrencyKostas Bousias, Chris R. Jesshope. 157-170 [doi]
- FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing UnitJih-Ching Chiu, Ren-Bang Lin. 171-185 [doi]
- Modularized Redundant Parallel Virtual File SystemSheng-Kai Hung, Yarsun Hsu. 186-199 [doi]
- Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar MicroarchitecturesJie Hu, Greg M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras. 200-214 [doi]
- A Fault-Tolerant Routing Strategy for Fibonacci-Class CubesZhang Xinhua, Peter Loh. 215-228 [doi]
- Embedding of Cycles in the Faulty HypercubeSun-Yuan Hsieh. 229-235 [doi]
- Improving the Performance of GCC by Exploiting IA-64 Architectural FeaturesCanqun Yang, Xuejun Yang, Jingling Xue. 236-251 [doi]
- An Integrated Partitioning and Scheduling Based Branch DecouplingPramod Ramarao, Akhilesh Tyagi. 252-268 [doi]
- A Register Allocation Framework for Banked Register Files with Access ConstraintsFeng Zhou, Junchao Zhang, Chengyong Wu, Zhaoqing Zhang. 269-280 [doi]
- Designing a Concurrent Hardware Garbage Collector for Small Embedded SystemsFlavius Gruian, Zoran A. Salcic. 281-294 [doi]
- Irregular Redistribution Scheduling by Partitioning MessagesChang Yu, Ching-Hsien Hsu, Kun-Ming Yu, Chiu-Kuo Liang, Chun-I Chen. 295-309 [doi]
- Making Power-Efficient Data Value PredictionsYong Xiao, Xingming Zhou, Kun Deng. 310-322 [doi]
- Speculative Issue LogicYou-Jan Tsai, Jong-Jiann Shieh. 323-335 [doi]
- Using Decision Trees to Improve Program-Based and Profile-Based Static Branch PredictionVeerle Desmet, Lieven Eeckhout, Koen De Bosschere. 336-352 [doi]
- Arithmetic Data Value SpeculationDaniel Kelly, Braden Phillips. 353-366 [doi]
- Exploiting Thread-Level Speculative Parallelism with Software Value PredictionXiao-Feng Li, Chen Yang, Zhao-Hui Du, Tin-Fook Ngai. 367-388 [doi]
- Challenges and Opportunities on Multi-core MicroprocessorJesse Fang. 389-390 [doi]
- Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable ArchitecturesK. S. Tham, Douglas L. Maskell. 391-404 [doi]
- A Switch Wrapper Design for SNA On-Chip-NetworkJiho Chang, JongSu Yi, JunSeong Kim. 405-414 [doi]
- A Configuration System Architecture Supporting Bit-Stream Compression for FPGAsMarco Torre, Usama Malik, Oliver Diessel. 415-428 [doi]
- Biological Sequence Analysis with Hidden Markov Models on an FPGAJacop Yanto, Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell. 429-439 [doi]
- FPGAs for Improved Energy Efficiency in Processor Based SystemsP. C. Kwan, C. T. Clarke. 440-449 [doi]
- Morphable Structures for Reconfigurable Instruction Set ProcessorsSiew Kei Lam, Deng Yun, Thambipillai Srikanthan. 450-463 [doi]
- Implementation of a Hybrid TCP/IP Offload Engine PrototypeHankook Jang, Sang-Hwa Chung, Soo-Cheol Oh. 464-477 [doi]
- Matrix-Star Graphs: A New Interconnection Network Based on Matrix OperationsHyeong-Ok Lee, Jong-Seok Kim, Kyoung-Wook Park, Jeonghyun Seo, Eunseuk Oh. 478-487 [doi]
- The Channel Assignment Algorithm on RP(k) NetworksFang ai Liu, Xinhua Wang, Liancheng Xu. 488-498 [doi]
- Extending Address Space of IP Networks with Hierarchical AddressingTingrong Lu, Chengcheng Sui, Yushu Ma, Jinsong Zhao, Yongtian Yang. 499-508 [doi]
- The Star-Pyramid Graph: An Attractive Alternative to the PyramidNavid Imani, Hamid Sarbazi-Azad. 509-519 [doi]
- Building a Terabit Router with XD NetworksHuaxi Gu, Zengji Liu, Jungang Yang, Zhiliang Qiu, Guochang Kang. 520-528 [doi]
- A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release TimeS. Suresh, V. Mani, S. N. Omkar, H.-J. Kim. 529-539 [doi]
- D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for ClustersZhen Liu, Jiaoying Shi, Haoyu Peng, Hua Xiong. 540-550 [doi]
- Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing ArchitecturesJongmyon Kim, D. Scott Wills, Linda M. Wills. 551-565 [doi]
- A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task SchedulingKyong Jung, Chanik Park. 566-579 [doi]
- Minimizing Power in Hardware/Software PartitioningWu Jigang, Thambipillai Srikanthan, Chengbin Yan. 580-588 [doi]
- Exploring Design Space Using Transaction Level ModelsYouhui Zhang, Liu Dong, Yu Gu, Dongsheng Wang. 589-599 [doi]
- Increasing Embedding Probabilities of RPRPs in RIN Based BISTDongSup Song, Sungho Kang. 600-613 [doi]
- A Practical Test Scheduling Using Network-Based TAM in Network on Chip ArchitectureJin-Ho Ahn, Byung-In Moon, Sungho Kang. 614-624 [doi]
- DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding TechniquesT. S. B. Sudarshan, Rahil Mir, S. Vijayalakshmi. 625-639 [doi]
- Efficient Architectural Support for Secure Bus-Based Shared Memory MultiprocessorKhaled Z. Ibrahim. 640-654 [doi]
- Covert Channel Analysis of the Password-Capability SystemDan Mossop, Ronald Pose. 655-668 [doi]
- Comparing Low-Level Behavior of SPEC CPU and Java WorkloadsAndy Georges, Lieven Eeckhout, Koen De Bosschere. 669-679 [doi]
- Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer ControlJong-Sun Kim, Ji-Yoon Yoo. 680-692 [doi]
- VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field MultipliersRavi Kumar Satzoda, Chip-Hong Chang. 693-706 [doi]
- Analysis of Real-Time Communication System with Queuing PriorityYunbo Wu, Zhishu Li, Yunhai Wu, Zhihua Chen, Tun Lu, Li Wang, Jianjun Hu. 707-713 [doi]
- FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc NetworksSai Gopalan, Gayathri Venkataraman, Sabu Emmanuel. 714-727 [doi]
- A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication SystemsSun-Kuk Noh. 728-735 [doi]
- Cache Leakage Management for Multi-programming WorkloadsChun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung. 736-749 [doi]
- A Memory Bandwidth Effective Cache Store Miss PolicyHou Rui, Fuxin Zhang, Weiwu Hu. 750-760 [doi]
- Application-Specific Hardware-Driven Prefetching to Improve Data Cache PerformanceMehdi Modarressi, Maziar Goudarzi, Shaahin Hessabi. 761-774 [doi]
- Targeted Data PrefetchingWeng-Fai Wong. 775-786 [doi]
- Area-Time Efficient Systolic Architecture for the DCTPramod Kumar Meher. 787-794 [doi]
- Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet TransformGab Jung, Seong Park, Jung Kim. 795-804 [doi]
- A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder ArchitecturesHimanshu Thapliyal, M. B. Srinivas. 805-817 [doi]
- Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded SystemIn-Su Yoon, Sang-Hwa Chung. 818-830 [doi]