Abstract is missing.
- Synthesizing FPGA Circuits from Parallel ProgramsSatnam Singh, David J. Greaves. 1 [doi]
- From Silicon to Science: The Long Road to Production Reconfigurable SupercomputingKeith D. Underwood. 2 [doi]
- The von Neumann Syndrome and the CS Education DilemmaReiner Hartenstein. 3 [doi]
- Optimal Unroll Factor for Reconfigurable ArchitecturesOzana Silvia Dragomir, Elena Moscu Panainte, Koen Bertels, Stephan Wong. 4-14 [doi]
- Programming Reconfigurable Decoupled Application Control Accelerator For Mobile SystemsSamar Yazdani, Joel Cambonie, Bernard Pottier. 15-26 [doi]
- DNA Physical Mapping on a Reconfigurable PlatformAdriano Idalgo, Nahri Moreano. 27-38 [doi]
- Hardware BLAST Algorithms with Multi-seeds Detection and Parallel ExtensionFei Xia, Yong Dou, Jinbo Xu. 39-50 [doi]
- Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAsChia-Tien Dan Lo, Yi-Gang Tai. 51-62 [doi]
- A Custom Processor for a TDMA Solver in a CFD ApplicationFilipe Oliveira, Castro M. P. Silva Santos, Fernando A. Castro, José C. Alves. 63-74 [doi]
- A High Throughput FPGA-based Floating Point Conjugate Gradient ImplementationAntonio Roldao Lopes, George A. Constantinides. 75-86 [doi]
- Physical Design of FPGA Interconnect to Prevent Information LeakageSumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin. 87-98 [doi]
- Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCsShane Santner, Wesley Peck, Jason Agron, David L. Andrews. 99-110 [doi]
- Run-time Adaptable Architectures for Heterogeneous Behavior Embedded SystemsAntonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro. 111-123 [doi]
- FPGA-based Real-time Super-Resolution on an Adaptive Image SensorMaria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides. 124-135 [doi]
- A Parallel Hardware Architecture for Image Feature DetectionVanderlei Bonato, Eduardo Marques, George A. Constantinides. 136-147 [doi]
- Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance SystemJosef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele. 148-158 [doi]
- A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable SystemsSlavisa Jovanovic, Camel Tanougast, Serge Weber. 159-170 [doi]
- A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable ProcessorVu Manh Tuan, Hideharu Amano. 171-182 [doi]
- Accelerating Speculative Execution in High-Level Synthesis with Cancel TokensHagen Gädke, Andreas Koch. 183-194 [doi]
- ARISE Machines: Extending Processors with Hybrid AcceleratorsNikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis. 195-206 [doi]
- The Instruction-Set Extension Problem: A SurveyCarlo Galuzzi, Koen Bertels. 207-218 [doi]
- An FPGA run-time parameterisable Log-Normal Random Number GeneratorPedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk. 219-230 [doi]
- Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGAChalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides. 231-242 [doi]
- Exploring Reconfigurable Architectures for Binomial-Tree Pricing ModelsQiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope. 243-253 [doi]
- Hybrid-Mode Floating-Point FPGA CORDIC Co-processorJie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong. 254-259 [doi]
- Multiplier-based double precision floating point divider according to the IEEE-754 standardVítor Silva, Rui Duarte, Mário P. Véstias, Horácio C. Neto. 260-265 [doi]
- Creating the World s Largest Reconfigurable Supercomputing System Based on the Scalable ALTIX System Infrastructure and Benchmarking Life-Science ApplicationsHaruna Cofer, Matthias Fouquet-Lapar, Timothy Gamerdinger, Christopher Lindahl, Bruce Losure, Alan Mayer, James Swoboda, Teruo Utsumi. 266-271 [doi]
- Highly efficient structure of 64-bit exponential function implemented in FPGAsMaciej Wielgosz, Ernest Jamro, Kazimierz Wiatr. 272-277 [doi]
- A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable ArchitecturesCarlo Galuzzi, Koen Bertels. 278-283 [doi]
- PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive ApplicationsFrank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich. 284-289 [doi]
- Stream Transfer Balancing Scheme Utilizing Multi-Path Routing in Networks on ChipPiotr Dziurzanski, Tomasz Maka. 290-295 [doi]
- Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case StudySteffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek. 296-301 [doi]
- Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable DevicesThomas Marconi, Yi Lu 0004, Koen Bertels, Georgi Gaydadjiev. 302-307 [doi]
- Data reallocation by exploiting FPGA configuration mechanismsOliver Sander, Lars Braun, Michael Hübner, Jürgen Becker. 308-313 [doi]
- A Networked, Lightweight and Partially Reconfigurable PlatformPierre Bomel, Guy Gogniat, Jean-Philippe Diguet. 314-319 [doi]
- Neuromolecularware -- A Bio-inspired Evolvable Hardware and Its Application to Medical DiagnosisYo-Hsien Lin, Jong-Chen Chen. 320-325 [doi]
- An FPGA Configuration Scheme for Bitstream ProtectionMasaki Nakanishi. 326-331 [doi]
- Lossless Compression for Space Imagery in a Dynamically Reconfigurable ArchitectureXiaolin Chen, Cedric Nishan Canagarajah, Raffaele Vitulli, José L. Núñez-Yáñez. 332-337 [doi]