Abstract is missing.
- FPGA Design Productivity - A Discussion of the State of the Art and a Research AgendaBrent E. Nelson. 1 [doi]
- Resiliency in Elemental ComputingJoseph Hassoun. 2 [doi]
- The Colour of Embedded ComputationIan Phillips. 3 [doi]
- A HyperTransport 3 Physical Layer Interface for FPGAsHeiner Litz, Holger Fröning, Ulrich Brüning. 4-14 [doi]
- Parametric Design for Reconfigurable Software-Defined RadioTobias Becker, Wayne Luk, Peter Y. K. Cheung. 15-26 [doi]
- Hardware/Software FPGA Architecture for Robotics ApplicationsJuan Carlos Moctezuma Eugenio, Miguel Arias-Estrada. 27-38 [doi]
- Reconfigurable Operator Based Multimedia Embedded ProcessorDaniel Menard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David. 39-49 [doi]
- A Protocol for Secure Remote Updates of FPGA ConfigurationsSaar Drimer, Markus G. Kuhn. 50-61 [doi]
- FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable ComputingKrzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker. 62-73 [doi]
- An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics ApplicationsMarco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello. 74-84 [doi]
- Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAsLuca Sterpone. 85-96 [doi]
- A Novel Local Interconnect Architecture for Variable Grain Logic CellKazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. 97-109 [doi]
- Dynamically Adapted Low Power ASIPsMateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro. 110-122 [doi]
- Fast Optical Reconfiguration of a Nine-Context DORGAMao Nakajima, Minoru Watanabe. 123-132 [doi]
- Heterogeneous Architecture Exploration: Analysis vs. Parameter SweepAsma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung. 133-144 [doi]
- On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega NetworksRicardo Ferreira, Alex Damiany, Julio Vendramini, Tiago Teixeira, João M. P. Cardoso. 145-156 [doi]
- A New Datapath Merging Method for Reconfigurable SystemMahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini. 157-168 [doi]
- Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC PlatformXu Guo, Patrick Schaumont. 169-180 [doi]
- Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher AlgorithmJaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro. 181-192 [doi]
- Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAsGang Zhou, Harald Michalik, László Hinsenkamp. 193-203 [doi]
- Compiling Techniques for Coarse Grained Runtime Reconfigurable ArchitecturesMythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan. 204-215 [doi]
- Online Task Scheduling for the FPGA-Based Partially Reconfigurable SystemsYi Lu 0004, Thomas Marconi, Koen Bertels, Georgi Gaydadjiev. 216-230 [doi]
- Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number GeneratorChalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides. 231-242 [doi]
- FPGA-Based Anomalous Trajectory Detection Using SOFMKofi Appiah, Andrew Hunter, Tino Kluge, Philip Aiken, Patrick Dickinson. 243-254 [doi]
- SORU: A Reconfigurable Vector Unit for Adaptable Embedded SystemsJosé Manuel Moya, Javier Rodriguez, Julio Martín, Juan Carlos Vallejo, Pedro Malagón, Álvaro Araujo, Juan-Mariano de Goyeneche, Agustín Rubio, Elena Romero, Daniel Villanueva, Octavio Nieto-Taladriz, Carlos A. López-Barrio. 255-260 [doi]
- A Parallel Branching Program Machine for Emulation of Sequential CircuitsHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura. 261-267 [doi]
- Memory Sharing Approach for TMR Softcore ProcessorYoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi. 268-274 [doi]
- The Need for Reconfigurable Routers in Networks-on-ChipDebora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin. 275-280 [doi]
- Transparent Dynamic Reconfiguration as a Service of a System-Level MiddlewareFernando Rincón, Jesús Barba, Francisco Moya, Juan Carlos López, Julio Dondo. 281-286 [doi]
- Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes DecoderSamar Yazdani, Thierry Goubier, Bernard Pottier, Catherine Dezan. 287-292 [doi]
- Tile-Based Fault Tolerant Approach Using Partial ReconfigurationAtsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Morisothi Yasunaga. 293-299 [doi]
- Regular Expression Pattern Matching Supporting Constrained RepetitionsSangKyun Yun, KyuHee Lee. 300-305 [doi]
- Accelerating Calculations on the RASC Platform: A Case Study of the Exponential FunctionMaciej Wielgosz, Ernest Jamro, Kazimierz Wiatr. 306-311 [doi]
- AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet CommunicationsJesús Lázaro, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga. 312-317 [doi]
- CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key CiphersDimitris Theodoropoulos, Alexandros Siskos, Dionisis Pnevmatikatos. 318-323 [doi]
- Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera SystemSirisak Leephokhanon, Theerayod Wiangtong. 324-329 [doi]
- Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined ArchitectureRaphael Weber, Achim Rettberg. 330-335 [doi]
- A Hardware Accelerated Simulation Environment for Spiking Neural NetworksBrendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire. 336-341 [doi]
- Survey of Advanced CABAC Accelerator Architectures for Future MultimediaYahya Jan, Lech Józwiak. 342-348 [doi]
- Real Time Simulation in Floating Point Precision Using FPGA ComputingBeniamin Apopei, Andy Mills, Tony Dodd, Haydn Thompson. 349-354 [doi]
- A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve CryptosystemBrian Baldwin, Richard Moloney, Andrew Byrne, Gary McGuire, William P. Marnane. 355-361 [doi]
- A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable SystemsRainer Buchty, David Kramer, Fabian Nowak, Wolfgang Karl. 362-367 [doi]
- Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical SimulatorTomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri. 368-373 [doi]
- ACCFS - Operating System Integration of Computational Accelerators Using a VFS ApproachAndreas Heinig, Jochen Strunk, Wolfgang Rehm, Heiko Schick. 374-379 [doi]
- A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA PlatformsMarkus Happe, Enno Lübbers, Marco Platzner. 380-385 [doi]