Abstract is missing.
- Nanocomputing with DelaysJosé A. B. Fortes. 3 [doi]
- Compositional Technique for Synthesising Multi-Phase Regular ArraysManju Manjunathaiah, Graham M. Megson. 7-16 [doi]
- A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process NetworksAlexandru Turjan, Bart Kienhuis, Ed F. Deprettere. 17-28 [doi]
- Model-Based Exploration of the Design Space for Heterogeneous Systems on ChipHolger Blume, H. Hübert, H. T. Feldkämper, Tobias G. Noll. 29-40 [doi]
- A Component Architecture for FPGA-Based, DSP System DesignGary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima. 41 [doi]
- Low Power Memory DesignWen-Tsong Shiue. 55-64 [doi]
- Reduced Power Consumption for MPEG Decoding with LNSMark G. Arnold. 65-75 [doi]
- A Model-Based Methodology for Application Specific Energy Efficient Data Path Design Using FPGAsSumit Mohanty, Seonil Choi, Ju-wook Jang, Viktor K. Prasanna. 76-87 [doi]
- Design Space Exploration for Energy-Efficient Secure Sensor NetworkLin Yuan, Gang Qu. 88 [doi]
- High-Radix Logarithm with Selection by RoundingJosé-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera. 101-110 [doi]
- An Analysis of the CORDIC Algorithm for Direct Digital Frequency SynthesisChang Yong Kang, Earl E. Swartzlander Jr.. 111-119 [doi]
- Evaluating Products of Non Linear Functions by Indirect Bipartite Table LookupDavid W. Matula, Alex Fit-Florea, Lee D. McFearin. 120-129 [doi]
- Efficient Conversion From Binary to Multi-Digit Multi-Dimensional Logarithmic Number Systems Using Arrays of Range Addressable Look-Up TablesRoberto Muscedere, Vassil S. Dimitrov, Graham A. Jullien, William C. Miller. 130 [doi]
- Predictable Instruction Caching for Media ProcessorsJames Irwin, David May, Henk L. Muller, Dan Page. 141-150 [doi]
- A Mathematical Model of Trace CacheAfzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen. 151-162 [doi]
- Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory ChipJeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim. 163-172 [doi]
- A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering ProcessorsWoo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang. 173 [doi]
- Fast Radix-4 Retimed Division with Selection by ComparisonsElisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli. 185-196 [doi]
- PAPA - Packed Arithmetic on a Prefix Adder for Multimedia ApplicationsNeil Burgess. 197-207 [doi]
- A Combined Interval and Floating-Point Comparator/SelectorAhmet Akkas. 208-217 [doi]
- Reviewing 4-to-2 Adders for Multi-Operand AdditionPeter Kornerup. 218 [doi]
- Implications of Programmable General Purpose Processors for Compression/Encryption ApplicationsByeong Kil Lee, Lizy Kurian John. 233-242 [doi]
- Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics PipelineChris Y. Chung, Ravi Managuli, Yongmin Kim. 243-252 [doi]
- Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained EnvironmentsRuby B. Lee, A. Murat Fiskiran, Zhijie Shi, Xiao Yang. 253-264 [doi]
- Polynomial Evaluation on Multimedia ProcessorsJulio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata. 265 [doi]
- Integrated Design of AES (Advanced Encryption Standard) Encrypter and DecrypterChih-Chung Lu, Shau-Yin Tseng. 277-285 [doi]
- Instruction Stream Mutation for Non-Deterministic ProcessorsJames Irwin, Dan Page, Nigel P. Smart. 286-295 [doi]
- A Novel Pipelined Threads Architecture for AES Encryption AlgorithmMehboob Alam, Wael M. Badawy, Graham A. Jullien. 296-302 [doi]
- On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption StandardGuido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri. 303 [doi]
- Matrix Engine for Signal Processing Applications Using the Logarithmic Number SystemE. I. Chester, John N. Coleman. 315-324 [doi]
- A VLSI Architecture for Object Recognition Using Tree MatchingK. Sitaraman, N. Ranganathan, Abdel Ejnioui. 325-334 [doi]
- Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOSSteven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall. 335-343 [doi]
- Optical Network Reconfiguration for Signal Processing ApplicationsRoger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy. 344 [doi]
- New Results on Array ContractionAlain Darte, Guillaume Huard. 359-370 [doi]
- A CORBA-Based GIS-T for Ambulance AssignmentTsai-Yun Liao, Ta-Yin Hu. 371-380 [doi]
- Advances in Bit Width Selection MethodologyDavid Cachera, Tanguy Risset. 381-390 [doi]
- Tradeoffs Between Quality of Results and Resource Consumption in a Recognition SystemMichael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O Sullivan, Mark A. Franklin. 391 [doi]