Abstract is missing.
- FPGA based system for real-time structure from motion computationMateusz Komorkiewicz, Tomasz Kryjak, Katarzyna Chuchacz-Kowalczyk, Pawel Skruch, Marek Gorgon. 1-7 [doi]
- Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platformsKevin J. M. Martin, Yvan Eustache, Jean-Philippe Diguet, Thanh Dinh Ngo, Emmanuel Casseau, Yaset Oliva. 1-2 [doi]
- FPGA implementations of HEVC Inverse DCT using high-level synthesisErcan Kalali, Ilker Hamzaoglu. 1-6 [doi]
- Fast and accurate power estimation for application-specific instruction set processors using FPGA emulationSebastian Hesselbarth, Gregor Schewior, Holger Blume. 1-7 [doi]
- Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video codingMaurizio Masera, Lorenzo Re Fiorentin, Maurizio Martina, Guido Masera, Enrico Masala. 1-6 [doi]
- FPGA-based real-time MFCC extraction for automatic audio indexing on FM broadcast dataGuy Wassi, Sylvain Iloga, Olivier Romain, Bertrand Granado. 1-6 [doi]
- FPGA-based detection of QRS complexes in ECG signalAmina El Hassen, Aymeric Histace, Mehdi Terosiet, Olivier Romain. 1-7 [doi]
- Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architecturesJens Brandenburg, Benno Stabernack. 1-8 [doi]
- Worst-case latency analysis of SDF-based parametrized dataflow MoCsMladen Skelin, Marc Geilen, Francky Catthoor, Sverre Hendseth. 1-6 [doi]
- Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on ChipStephan Werner 0002, Bernhard Stiehle, Jürgen Becker. 1-6 [doi]
- Robot navigation based on an efficient combination of an extended A∗ algorithm, bird's eye view and image stitchingJens Rettkowski, David Gburek, Diana Göhringer. 1-8 [doi]
- Reliable NCO carrier generators for GPS receiversMourad Dridi, Mohamed Mourad Hafidhi, Chris Winstead, Emmanuel Boutillon. 1-5 [doi]
- Hardware implementation of a soft cancellation decoder for polar codesGuillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet. 1-8 [doi]
- Dynamic power evaluation of LTE wireless baseband processing on FPGAJordane Lorandel, Jean-Christophe Prévotet, Maryline Hélard. 1-6 [doi]
- Image tiling for embedded applications with non-linear constraintsVítor Schwambach, Sébastien Cleyet-Merle, Alain Issard, Stéphane Mancini. 1-8 [doi]
- Selecting most profitable instruction-set extensions using ant colony heuristicShanshan Wang, Chenglong Xiao, Wanjun Liu, Emmanuel Casseau, Xiao Yang. 1-7 [doi]
- Exploring custom heterogeneous MPSoCs for real-time neural signal decodingPaolo Meloni, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo. 1-8 [doi]
- Fast and efficient signals recovery for deterministic compressive sensing: Applications to biosignalsAndrianiaina Ravelomanantsoa, Hassan Rabah, Amar Rouane. 1-6 [doi]
- Reducing the impact of internal upsets inside the correlation process in GPS ReceiversMohamed Mourad Hafidhi, Emmanuel Boutillon, Chris Winstead. 1-5 [doi]
- Implementation of IEEE-802.11a/g receiver blocks on a coarse-grained reconfigurable arraySajjad Nouri, Waqar Hussain, Jari Nurmi. 1-8 [doi]
- Real-time correlation for locating systems utilizing heterogeneous computing architecturesMarc Reichenbach, Maximilian Kasparek, Mohammad Alawieh, Konrad Häublein, Dietmar Fey. 1-8 [doi]
- Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions supportBenno Stabernack, Jan Moller, Jan Hahlbeck, Jens Brandenburg. 1-2 [doi]
- BM3D image denoising using heterogeneous computing platformsSampsa Sarjanoja, Jani Boutellier, Jari Hannuksela. 1-8 [doi]
- Implementation of a Fast Fourier transform algorithm onto a manycore processorJulien Hascoet, Jean-François Nezan, Andrew Ensor, Benoît Dupont de Dinechin. 1-7 [doi]