Abstract is missing.
- Mapping and Scheduling in a Shared Parallel Environment Using Distributed Hierarchical ControlDror G. Feitelson, Larry Rudolph. 1-8
- Scheduling to Account for Interprocessor Communication within Interconnection-Constrained Processor NetworksGilbert C. Sih, Edward A. Lee. 9-16
- Dynamic Task Allocation on Shared Memory Multiprocessor SystemsJiahuang Ji, Menkae Jeng. 17-21
- Adaptive Optimal Load Balancing of Loosely Coupled Processors with Arbitrary Service Time DistributionsRamaswamy Venkatesh, Galigekere R. Dattatreya. 22-25
- Estimating the Performance Advantages of Relaxing Consistency in a Shared Memory MultiprocessorJosep Torrellas, John L. Hennessy. 26-34
- Hardware Barrier Synchronization: Static Barrier MIMD (SBM)Matthew T. O Keefe, Henry G. Dietz. 35-42
- Hardware Barrier Synchronization: Dynamic Barrier MIMD (DBM)Matthew T. O Keefe, Henry G. Dietz. 43-46
- Implementing Sequential Consistency in Cache-Based SystemsSarita V. Adve, Mark D. Hill. 47-50
- Optimizing Task Migration Transfers Using Multistage Cube NetworksThomas Schwederski, Howard Jay Siegel, Thomas L. Casavant. 51-58
- Round-Robin Load Balancing in a Shared Memory Multiprocessor SystemMingfang Wang, Behrooz Shirazi. 59-66
- A Scheduling Strategy for Shared Memory MultiprocessorsLal George. 67-71
- An Approximate Algorithm for the Partitionable Independent Task Scheduling ProblemKrishna P. Belkhale, Prithviraj Banerjee. 72-75
- On Methods for Fast and Efficient Parallel Memory AccessC. S. Raghavendra, Rajendra V. Boppana. 76-83
- Minimizing Memory Requirements for Partitionable SIMD/SPMD MachinesMark A. Nichols, Howard Jay Siegel, Henry G. Dietz, Russell W. Quong, Wayne G. Nation. 84-91
- Distributed Linear Hashing for Main Memory DatabasesCharles Severance, Sakti Pramanik. 92-95
- Use of Perfect Hashing in a Paged Memory Management UnitForbes J. Burkowski, Gordon V. Cormack. 96-100
- Time-Optimal and Conflict-Free Mappings of Uniform Dependence Algorithms into Lower Dimensional Processor ArraysWeijia Shang, José A. B. Fortes. 101-110
- Optimal Granularity of Grid Iteration ProblemsZhimin Tang, Guo-Jie Li. 111-118
- Job Scheduling in PMCS Using a 2DBS as the System Partitioning SchemeKeqin Li, Kam-Hoi Cheng. 119-122
- Multi-Phase Systolic Architectures for Spectral DecompositionK. J. Ray Liu, Kung Yao. 123-126
- Asynchronous Parallel Processing of Object Bases Using Multiple WavefrontsArun K. Thakore, Stanley Y. W. Su, Herman Lam, Dennis G. Shea. 127-135
- Development of a Partitioned, Replicated Data Server in FLAMEFlavio De Paoli, Mehdi Jazayeri. 136-139
- A Bus-Connected Multiprocessor for Run-Length-Based Image ProcessingKiyoshi Nakabayashi. 140-144
- Formal Synthesis of a Parallel Architectures from Recursive EquationsKhaled M. Elleithy, Magdy A. Bayoumi. 145-148
- Evaluation of New Architectural Features in a Massively Parallel SIMD MachineEdward W. Davis, Joann M. Jennings. 149-152
- Transient Models of Bus-Based MultiprocessorsAnastasios A. Economides, Michel Dubois. 153-160
- A Replicate Workload Framework to Study Performance Degradation in Shared-Memory MultiprocessorsArun K. Nanda, Honda Shing, Ten H. Tzen, Lionel M. Ni. 161-168
- Cost-Performance Tradeoffs in Manhattan Street Network versus 2-D TorusTein Y. Chung, Dharma P. Agrawal. 169-172
- Hit Ratio and Communication Cost of Shared Data in a Cache-Based System with Multistage Interconnection NetworkSyed Masud Mahmud, Venkat Tiruveedhula. 173-176
- On System Effectiveness Evaluation of Real-Time Parallel and Distributed Computing SystemsAnup Kumar, Dharma P. Agrawal. 177-180
- A Formal Model of the Processor Memory InterfaceSamuel Ho, Lawrence Snyder. 181-184
- Diagnosing Parallel Program Speedup Limitations Using Resource Contention ModelsThin-Fong Tsuei, Mary K. Vernon. 185-189
- The Performance of a Faulty Multistage Interconnection Network with Diverting Switches and Correction LinksLance Kurisaki, Tomás Lang. 190-193
- On Designing Hardware-Efficient Parallel Architectures for the Class NCJavaid Aslam. 194-197
- A Performance Evaluation Methodology for Coupled Multiple SupercomputersLishing Liu, Jih-Kwon Peir. 198-202
- Load Balancing on the Hypercube and Related NetworksJoseph JáJá, Kwan Woo Ryu. 203-210
- A Partial Compaction Scheme for Processor Allocation in Hypercube MultiprocessorsChih-Hao Huang, Jie-Yong Juang. 211-217
- The Efficiency of the Folded Hypercube in Subcube AllocationShahram Latifi. 218-221
- An Analysis of Fixed-Assignment Hypercube PartitioningFrank J. Weil, Leah H. Jamieson, Edward J. Delp. 222-225
- Techniques for Mapping Deterministic Algorithms onto Multi-Level SystemsSotirios G. Ziavras. 226-233
- Optimal Mapping of Neural Networks on MulticomputersBenjamin W. Wah, Lon-Chan Chu. 234-241
- Parallel Architectures for a Class of Neural Net Based AlgorithmsWeicheng Shen. 242-246
- Implementation of Neural Network Algorithms on the P:::3::: Parallel Associative ProcessorKonstantinos I. Diamantaras, David L. Heine, Isaac D. Scherson. 247-250
- Reaching a Fault Detection AgreementShu-Chin Wang, Yeh-Hao Chin, Kuo-Qin Yan. 251-258
- On Parallel Algorithms for Single-Fault DiagnosisNageswara S. V. Rao. 259-266
- Diagnostic Power of Four Basic System-Level Diagnosis Strategies for HypercubesAlireza Kavianpour, K. H. Kim. 267-271
- Forward Recovery Using Checkpointing in Parallel SystemsJunsheng Long, W. Kent Fuchs, Jacob A. Abraham. 272-275
- Full Bandwidth Communications for Folded HypercubesChing-Tien Ho. 276-280
- A Performance Comparison of Routing Algorithms for Hierarchical Hypercube Multicomputer NetworksSivarama P. Dandamudi. 281-285
- Optimal Routing of Bit-Permutes on Hypercube MachinesC. S. Raghavendra, M. A. Sridhar. 286-290
- The Effectiveness of Combining in Reducing Hot-Spot Contention in Hypercube MulticomputersSivarama P. Dandamudi, Derek L. Eager. 291-295
- A Comparison of Circuit and Packet Switching in a Fiber-Optic HypercubeTed H. Szymanski. 296-300
- Preemptive Job Scheduling on a HypercubeYahui Zhu, Mohan Ahuja. 301-304
- A Performance Comparison of Directory-based and Timestamp-based Cache Coherence SchemesSang Lyul Min, Jean-Loup Baer. 305-311
- Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence SchemesAnoop Gupta, Wolf-Dietrich Weber, Todd C. Mowry. 312-321
- Cache Support for the Asynchronous PRAMPhillip B. Gibbons. 322-325
- Modeling of Live Lines and True Sharing in Multi-Cache Memory SystemsAbraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan. 326-330
- Self-Routing and Route Balancing in Connection NetworksBarry G. Douglass, A. Yavuz Oruç. 331-337
- Permutation Capability of Multistage Interconnection NetworksCalvin J. A. Hsia, C. Y. Roger Chen. 338-346
- On Necklaces in Shuffle-Exchange and de Bruign NetworksRobert A. Rowley, Bella Bose. 347-350
- On Routing a Faulty Benes NetworkStephen K. Wysham, Tse-Yun Feng. 351-354
- The Design and Evaluation of the Hierarchical Cubic NetworkKanad Ghose, Kiran Raghavendra Desai. 355-362
- A Generalization of the Binary Shuffle-Exchange Architecture for Non-Power-of-Two System SizesKrishnan Padmanabhan. 363-371
- The Generalized Folding-CubeSang-Bang Choi, Arun K. Somani. 372-375
- On Bitonic Sorting NetworksKenneth E. Batcher. 376-379
- Orthogonal Graphs and the Analysis and Construction, of a Class of Multistage Interconnection NetworksIsaac D. Scherson. 380-387
- PAFMV-Pairwise Asynchronous MultigridSteve Franks, Bruce M. McMillin, Rashi Khanna. 388-392
- U-Star: A Modular Indirect Star Network Based on (2 X 2) SwitchesWen-Shyen E. Chen, Kyungsook Y. Lee, Ming T. Liu. 393-396
- A New Class of Three-Stage Switching Networks and Their Routing PropertiesBarry G. Douglass. 397-400
- Hotspot Contention in Non-Blocking Multistage Interconnection NetworksRobert L. Lesher, Matthew Thazhuthaveetil. 401-404
- A Decoupled Graph/Computation Data-Driven Architecture with Variable-Resolution ActorsParaskevas Evripidou, Jean-Luc Gaudiot. 405-414
- A Program Allocation Scheme for Data Flow ComputersAli R. Hurson, Ben Lee, Behrooz Shirazi, Mingfang Wang. 415-423
- Performance Degradation in Large Wormhole-Routed Interprocessor Communication NetworksSuresh Chittor, Richard J. Enbody. 424-428
- Uniform-Cost Communication in Scalable MultiprocessorsRichard J. Lipton, Dimitrios N. Serpanos. 429-432
- Fault-Tolerant Cube-Connected Cycles Structures Through Dimensional SubstitutionNian-Feng Tzeng, Sourav Bhattacharya, Po-Jen Chuang. 433-440
- A Fault Tolerant Batcher NetworkHideharu Amano. 441-444
- Fault-Tolerant Task Mapping Algorithms for MIN-Based MultiprocessorsMazin S. Algudady, Chita R. Das, Woei Lin. 445-448
- A New Class of Optimal VLSI Networks for Multidimensional TransformsHussein M. Alnuweiri. 449-456
- SETH: A VLSI Chip for the Real-Time Information Dispersal and Retrieval for Security and Fault-ToleranceAzer Bestavros. 457-464
- A Linear Systolic Algorithm for Finding Bridges on an Undirected Connected GraphHsien-Fen Hsieh, Shing-Tsaan Huang, Su-Chu Hsu. 465-469
- Parallel Processing and Hardware Acceleration for Synthesis of VLSI Devices from Behavioral ModelsCharles E. Stroud, Ahmed E. Barbour. 470-473
- Parallel Knowledge Processing on SNAPDan I. Moldovan, Wing Lee, Changwa Lin, Sang-Hwa Chung. 474-481
- Parallel Knowledge Classification on SNAPJun-Tae Kim, Dan I. Moldovan. 482-488
- On Balanced Synchronous Parallel Computers for AIDaniel P. Miranker, Archie D. Andrews. 489-493
- Performance Evaluation of Clusters of NETRA: An Architecture for Computer Vision SystemsAlok N. Choudhary, Janak H. Patel. 494-497
- Evaluation of the Communication Network of POOMAWiljo J. van Beek, Rob A. H. Twist, Marnix C. Vlot. 498-507
- Hardware Support for Message Routing in a Distributed Memory MulticomputerJiun-Ming Hsu, Prithviraj Banerjee. 508-515
- Optimizing the Communication Architecture of a Hierarchical Parallel ProcessorStephen A. Mabbs, Kevin E. Forward. 516-520
- Constraint Based Evaluation of Multicomputer NetworksSeth Abraham, Krishnan Padmanabhan. 521-525
- SPLASH: A Reconfigurable Linear Logic ArrayMaya Gokhale, William Holmes, Andrew Kopser, Dick Kunze, Daniel P. Lopresti, Sara Lucas, Ronald Minnich, Peter Olsen. 526-532
- Task Flow Computer ArchitectureRobert W. Horst. 533-540
- A Fine-Grain Bit-Parallel, Word-Parallel, Massively-Parallel Associative ProcessorIsaac D. Scherson, David A. Kramer, Brian D. Alleyne. 541-544
- Systolic Associative MemoriesBehrooz Parhami. 545-548
- Highly Parallel Virtual Memory Management on the TC2000David R. Barach, Robert Wells, Thomas Uban, James Gibson. 549-550
- A Dynamic Partitioning Strategy on Distributed Memory SystemsMin-You Wu, Wei Shu. 551-552
- A Scalable Coherent Cache System With Incomplete Directory StateEugene D. Brooks III, Joseph E. Hoag. 553-554
- Data Type Coherency in Heterogeneous Shared Memory MultiprocessorsMichael W. Strevell, Harvey G. Cragon. 555-556
- Reliability in Bus Structured and Completely Connected Distributed SystemsBrian Waldecker, Mario J. Gonzalez Jr.. 557-558
- Modeling Availability of Parallel ComputersSalim Hariri, A. Gaber Mohamed, Hasan B. Mutlu. 559-560
- A Tree Structured Hierarchical Memory MultiprocessorJeff D. Martens, D. N. Jayasimha. 561-562
- Comparing Parallelism Extraction Techniques: Superscalar Processors, Pipelined Processors, and MultiprocessorsDavid J. Lilja, Pen-Chung Yew. 563-564
- A Hierarchical Approach for the Design of Two-Dimensional Fault-Tolerant Systolic ArraysTein-Hsiang Lin, Adly T. Fam. 565-566
- Grain Size Oriented Pipeline Machine - GRAPEHiroshi Nishikawa, Kazuo Sakushima, Takashi Hamada, Motohiro Misawa, Katsura Kawakami. 567-568
- Local v Global Strategies for Dynamic Load BalancingMarc Willebeek-LeMair, Anthony P. Reeves. 569-570
- On Subcube Allocation and Relinquishment Schemes for Hypercube Connected MultiprocessorSwie-Tsing Tan, David Hung-Chang Du. 571-572
- Task Allocation on the Hypercube MultiprocessorWin-Tsung Lo, Satish K. Tripathi, Dipak Ghosal. 573-574
- Task Duplication Static-Scheduling for Multiprocessor Systems with Non-Fixed Execution Time TasksEmilio Luque, Ana Ripoll, Porfidio Hernández, Tomàs Margalef. 575-576
- A Data Flow Architecture ImplementationZhenqiang Fan, Kam-Hoi Cheng. 577-578
- Communication Aspects of the Cube Connected CyclesDikran S. Meliksetian, C. Y. Roger Chen. 579-580
- Structure of Digit Permutation NetworksAbdou Youssef, Bruce W. Arden. 581-582
- n:::+:::^-Cube: The Extra Dimensional n-CubeShyh-Kwei Chen. 583-584
- Reliability Analysis of Two Classes of Double-Tree Network-Based MultiprocessorsBernard L. Menezes, Ramakrishna Thurimella. 585-586
- SIMD Neural Net Mapping on MIMD ArchitecturesPeter Wohl, Thomas W. Christopher. 587-588
- Finding the Shortest Path in ESMSS NetworkZhiyong Liu, Jia-Huai You. 589-590
- A Multi-Ring Transputer Network for the Arbitrary Rotation of Raster ImagesHamid R. Arabnia. 591-592
- On Optimal Evaluation of Conjunctive Queries in Parallel EnvironmentsWon S. Lee, Rangasami L. Kashyap, Phillip C.-Y. Sheu. 593-594
- Parallel Addition Using Pipeline StructureReza Hashemian. 595-596
- A Generalized Simultaneous Access Dictionary MachineZhenqiang Fan, Kam-Hoi Cheng. 597-598
- A Parallel Optimal Arc Consistency AlgorithmJun Gu, Rok Sosic. 599-600
- A Bit-Sliced Special Purpose Unit for Relational Database Aggregation OperationsMahdi Abdelguerfi, H. Munaf. 601-602
- Coprocessor Parallel Architecture for CompilationYaohon Chu, Kozo Itano. 603-604
- SPARCS: A System for Parallel Architecture SimulationNimish R. Shah, Lalit M. Patnaik. 605-606
- A Fine-Grained Parallel Architecture for Graph ReductionAloke Guha. 607-608
- The Machine Paradigm of Xputers and its Application to Digital Signal Processing AccelerationReiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber. 609-610
- An Area-Efficient Register Alias Table for Implementing HPSMichael Butler, Yale N. Patt. 611-612
- Evaluation of Inter-processor Communication in the KL1 Implementation on the Multi-PSIKatsuto Nakajima, Nobuyuki Ichiyoshi. 613-614
- Livermore Loops on the Connection MachineMichael A. Young. 615-616
- A Linear Systolic Array for Transitive Closure ProblemsJean Frédéric Myoupo. 617-618
- An Integral Microcontroller Architecture Designed by Using the Register Transfer Language for VLSI ChipsIrving S. Reed, Xuemin Chen, Trieu-Kien Truong. 619-620
- Dynamic Full Access in Fault Tolerant Multistage Interconnection NetworksVijay P. Kumar, S. J. Wang. 621-630