Abstract is missing.
- McCharts and Multiclock FSMs for modeling large scale systemsIvan Radojevic, Zoran A. Salcic, Partha S. Roop. 3-12 [doi]
- Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive DesignCheng-Hong Li, Rebecca L. Collins, Sampada Sonalkar, Luca P. Carloni. 13-22 [doi]
- Formal verification of an optimizing compilerXavier Leroy. 25 [doi]
- Computing Invariants for Parameter AbstractionYi Lv, Huimin Lin, Hong Pan. 29-38 [doi]
- Executable Analysis using Abstract Interpretation with Circular Linear ProgressionsRathijit Sen, Y. N. Srikant. 39-48 [doi]
- Scheduling as Rule CompositionNirav Dave, Arvind, Michael Pellauer. 51-60 [doi]
- Type Inference for IP CompositionDeepak Mathaikutty, Sandeep K. Shukla. 61-70 [doi]
- From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM ProtocolsMan Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks. 71-80 [doi]
- Local Causal Reasoning of a Safety-Critical Subway SystemEdgar G. Daylight, Sandeep K. Shukla. 83-84 [doi]
- Multi-Level Assertion-Based DesignHans Eveking, Martin Braun, Martin Schickel, Martin Schweikert, Volker Nimbler. 85-86 [doi]
- Extended Architecture Analysis Description Language for Software Product Line Approach in Embedded SystemsYoungseok Oh, Danhyung Lee, Sungwon Kang, Jihyun Lee. 87-88 [doi]
- MEMOCODE 2007 Co-Design ContestForrest Brewer, James C. Hoe. 91-94 [doi]
- VT Matrix Multiply Design for MEMOCODE 07Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumit Ahuja, Sandeep K. Shukla. 95-96 [doi]
- Hardware Acceleration of Matrix Multiplication on a Xilinx FPGANirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan. 97-100 [doi]
- Towards a Unified Execution Model for Transactions in TLMBernhard Niemann, Christian Haubelt. 103-112 [doi]
- Towards Equivalence Checking Between TLM and RTL ModelsNicola Bombieri, Franco Fummi, Graziano Pravadelli, João Marques-Silva. 113-122 [doi]
- Verification Driven Formal Architecture and Microarchitecture ModelingYogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin. 123-132 [doi]
- Proving What Programs Do NotBertrand Meyer. 135 [doi]
- Software/Hardware Engineering with the Parallel Object-Oriented Specification LanguageBart D. Theelen, Oana Florescu, Marc Geilen, Jinfeng Huang, P. H. A. van der Putten, Jeroen Voeten. 139-148 [doi]
- One-dimensional Search Algorithms for Hardware/Software PartitioningWu Jigang, Thambipillai Srikanthan, Guang Chen. 149-158 [doi]
- A Methodology for Automating Co-Scheduling for Reconfigurable Computing SystemsProshanta Saha, Tarek A. El-Ghazawi. 159-168 [doi]
- Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer ProtocolsGeoffrey M. Brown, Lee Pike. 171-180 [doi]
- Combining Multi-Valued Logics in SAT-based ATPG for Path Delay FaultsStephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel. 181-187 [doi]
- Easier and More Informative Vacuity ChecksHana Chockler, Ofer Strichman. 189-198 [doi]
- Bringing Hardware and Software Closer Together with Termination AnalysisByron Cook. 201 [doi]