Abstract is missing.
- Systematic testing for control applicationsRupak Majumdar, Indranil Saha, Zilong Wang. 1-10 [doi]
- Message from the chairsKlaus Schneider, Barbara Jobstmann, Luca P. Carloni, Jens Brandt. 1-3 [doi]
- A design flow based on modular refinementNirav Dave, Man Cheuk Ng, Michael Pellauer, Arvind. 11-20 [doi]
- Designing application specific circuits with concurrent C# programsDavid J. Greaves, Satnam Singh. 21-30 [doi]
- ATLAS: Automatic Term-level abstraction of RTL designsBryan A. Brady, Randal E. Bryant, Sanjit A. Seshia, John W. O Leary. 31-40 [doi]
- A flexible schema for generating explanations in lazy theory propagationRoberto Bruttomesso, Edgar Pek, Natasha Sharygina. 41-48 [doi]
- Numerical stability analysis of floating-point computations using software model checkingFranjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta. 49-58 [doi]
- Modular verification of synchronization with reentrant locksTevfik Bultan, Fang Yu, Aysu Betin-Can. 59-68 [doi]
- Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID)Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer. 69-72 [doi]
- A regular expression matching using non-deterministic finite automatonHiroshi Nakahara, Tsutomu Sasao, Munehiro Matsuura. 73-76 [doi]
- FPGA-based combined architecture for stream categorization and intrusion detectionSunil Shukla, Rodric Rabbah, Martin Vorbach. 77-80 [doi]
- High-throughput stream categorization and intrusion detection on GPUMohammad-Hassan Khabbazian, Hassan Eslami, Ehsan Totoni, AmadReza Khadem. 81-84 [doi]
- Using hardware-software codesign language to implement CANSCIDOleg Medvedev, Ilya Posov. 85-88 [doi]
- A hardware accelerated system for deep packet inspectionAdarsha Rao, Pramod Udupa. 89-92 [doi]
- CANSCID-CUDAMichael Steffen, Veerendra Allada, Phillip Jones, Joseph Zambreno. 95-98 [doi]
- Team [Ii][Ss][Uu][0-2]{4} design overview: MEMOCODE 2010 design contestSudhanshu Vyas, Pooja Mhapsekar, Aditya Ashok, Moinuddin Sayed, Avinash Srinivasa, Gunjan Pandey, Adam Jackson, Matthew Nelson, Anand Saggi, Harini Sundararaman, Phillip H. Jones. 99-102 [doi]
- Enhancing the assertion-based verification of TLM designs with reentrancyLaurence Pierre, Luca Ferro. 103-112 [doi]
- Proving transaction and system-level properties of untimed SystemC TLM designsDaniel Große, Hoang M. Le, Rolf Drechsler. 113-122 [doi]
- Monitoring temporal SystemC propertiesDeian Tabakov, Moshe Y. Vardi. 123-132 [doi]
- Power emulation: Methodology and applications for HW/SW power optimizationJosef Haid, Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiss. 133-138 [doi]
- Understanding loops: The influence of the decomposition of Karp, Miller, and WinogradAlain Darte. 139-148 [doi]
- Elastic systemsJordi Cortadella, Marc Galceran Oms, Michael Kishinevsky. 149-158 [doi]
- Predictable multithreading of embedded applications using PRET-CSidharta Andalam, Partha S. Roop, Alain Girault. 159-168 [doi]
- Feldspar: A domain specific language for digital signal processing algorithmsEmil Axelsson, Koen Claessen, Gergely Dévai, Z. Horváth, Karin Keijzer, Bo Lyckegård, Anders Persson, Mary Sheeran, Josef Svenningsson, A. Vajda. 169-178 [doi]
- A formal executable semantics of VerilogPatrick O Neil Meredith, Michael Katelman, José Meseguer, Grigore Rosu. 179-188 [doi]
- Minimizing back pressure for latency insensitive system synthesisBin Xue, Sandeep K. Shukla, S. S. Ravi. 189-198 [doi]
- LTSs for translation validation of (multi-clocked) SIGNAL specificationsJulio C. Peralta, Thierry Gautier, Loïc Besnard, Paul Le Guernic. 199-208 [doi]
- Compilation of imperative synchronous programs with refined clocksMike Gemunde, Jens Brandt, Klaus Schneider. 209-218 [doi]