Table of Contents

• Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAMHe Zhang, Wang Kang, Tingting Pang, Weifeng Lv, Youguang Zhang, Weisheng Zhao. 1-6 [doi]
• Capacitor based SneakPath compensation circuit for transistor-less ReRAM architecturesA. Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean Michel Portal. 7-12 [doi]
• TFET NDR skewed inverter based sensing methodNavneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Sorin Cotofana, Costin Anghel. 13-14 [doi]
• Inversion optimization in Majority-Inverter GraphsEleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 15-20 [doi]
• A compare-and-select error tolerant scheme for nonvolatile processorsZhibo Wang, Rui Hua, Yongpan Liu, Huazhong Yang. 21-22 [doi]
• np-ECC: Nonadjacent position error correction code for racetrack memoryXiaoyang Wang, Chao Zhang, Xian Zhang, Guangyu Sun. 23-24 [doi]
• Towards automatic thermal network extraction in 3D ICsMingyu Li, Santosh Khasanvis, Jiajun Shi, Sachin Bhat, Mostafizur Rahman, Csaba Andras Moritz. 25-30 [doi]
• Design of approximate Redundant Binary multipliersTian Cao, Weiqiang Liu, Chenghua Wang, Xiao-Ping Cui, Fabrizio Lombardi. 31-36 [doi]
• Error Correction Code protected Data Processing UnitsNicoleta Cucu Laurenciu, T. Gupta, V. Savin, Sorin Dan Cotofana. 37-42 [doi]
• Synthesizing HDL to memristor technology: A generic frameworkH. A. Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels. 43-48 [doi]
• Energy management on DVS based coarse-grained reconfigurable platformPeng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei. 49-54 [doi]
• SSO-LSM: A Sparse and Self-Organizing architecture for Liquid State Machine based neural processorsYingyezhe Jin, Yu Liu, Peng Li. 55-60 [doi]
• Nonvolatile online CMOS trimming with magnetic tunnel junctionsSumit Dutta, Michael Price, Marc A. Baldo. 61-66 [doi]
• Combining a volatile and nonvolatile memristor in artificial synapse to improve learning in Spiking Neural NetworksMahyar Shahsavari, Pierre Falez, Pierre Boulet. 67-72 [doi]
• Evaluation of spin-Hall-assisted STT-MRAM for cache replacementLiang Chang, Zhaohao Wang, Yuqian Gao, Wang Kang, Youguang Zhang, Weisheng Zhao. 73-78 [doi]
• A supply voltage-dependent variation aware reliability evaluation modelBo Yang, Emanuel M. Popovici, Michael Alan Quille, Andreas Amann, Sorin Cotofana. 79-84 [doi]
• MECRO: A local processing computer architecture based on memristor crossbarLei Xie, Muhammad Adib Bin Haron. 85-90 [doi]
• Mosaic: A scheme of mapping non-volatile Boolean logic on memristor crossbarLei Xie. 91-96 [doi]
• Synthesis of memristive circuits based on stateful IMPLY gates using an evolutionary algorithm with a correction functionXiaoxiao Wang, Robin Tan, Marek A. Perkowski. 97-102 [doi]
• Multi-context non-volatile content addressable memory using magnetic tunnel junctionsErya Deng, Lorena Anghel, Guillaume Prenat, Weisheng Zhao. 103-108 [doi]
• A memristor-based compressive sensing architectureFengyu Qian, Yanping Gong, Guoxian Huang, Kiarash Ahi, Mehdi Anwar, Lei Wang. 109-114 [doi]
• Accelerate context switch by racetrack-SRAM hybrid cellsWeiqi Zhang, Chao Zhang, Guangyu Sun. 115-116 [doi]
• Sleep stage classification with stochastic Bayesian inferenceLaurie E. Calvet, Joseph S. Friedman, Damien Querlioz, Pierre Bessière, Jacques Droulez. 117-122 [doi]
• A novel circuit design of true random number generator using magnetic tunnel junctionYou Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao. 123-128 [doi]
• An STT-MRAM based strong PUFSoroush Khaleghi, Paolo Vinella, Soumya Banerjee, Wenjing Rao. 129-134 [doi]
• Improved circuit model for all-spin logicMeshal Alawein, Hossein Fariborzi. 135-140 [doi]
• Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropyZhizhong Zhang, Yue Zhang, Lei Yue, Li Su, Yichuan Shi, Youguang Zhang, Weisheng Zhao. 141-142 [doi]
• A spin Hall effect-based multi-level cell for MRAMQian Shi, Zhaohao Wang, Yuqian Gao, Liang Chang, Wang Kang, Youguang Zhang, Weisheng Zhao. 143-144 [doi]
• Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOSJiajun Shi, Mingyu Li, Santosh Khasanvis, Mostafizur Rahman, Csaba Andras Moritz. 145-150 [doi]
• Fine-grained 3-D CMOS concept using stacked horizontal nanowireNaveen Kumar Macha, Md Arif Iqbal, Mostafizur Rahman. 151-152 [doi]
• Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devicesDeliang Fan. 153-158 [doi]
• Approximate in-memory Hamming distance calculation with a memristive associative memoryMohammad Mahmoud A. Taha, Walt Woods, Christof Teuscher. 159-164 [doi]
• Skeleton-based design and simulation flow for Computation-in-Memory architecturesJintao Yu, Razvan Nane, Adib Haron, Said Hamdioui, Henk Corporaal, Koen Bertels. 165-170 [doi]
• Memory Processing Unit for in-memory processingRotem Ben Hur, Shahar Kvatinsky. 171-172 [doi]
• Stochastic spintronic device based synapses and spiking neurons for neuromorphic computationDeming Zhang, Lang Zeng, Youguang Zhang, Weisheng Zhao, Jacques-Olivier Klein. 173-178 [doi]
• A memristor network with coupled oscillator and crossbar towards L2-norm based machine learningLeibin Ni, Hantao Huang, Hao Yu. 179-184 [doi]
• Exploring the optimal learning technique for IBM TrueNorth platform to overcome quantization lossHsin-Pai Cheng, Wei Wen, Chang Song, Beiye Liu, Hai Li, Yiran Chen. 185-190 [doi]
• A comparative evaluation of approximate multipliersHonglan Jiang, Cong Liu, Naman Maheshwari, Fabrizio Lombardi, Jie Han. 191-196 [doi]
• A fully parallel approximate CORDIC designLinbin Chen, Fabrizio Lombardi, Jie Han, Weiqiang Liu. 197-202 [doi]
• Approximate computing in MOS/spintronic non-volatile full-adderHao Cai, You Wang, Lirida A. B. Naviner, Zhaohao Wang, Weisheng Zhao. 203-208 [doi]