Abstract is missing.
- Enabling Technology for On-Chip Interconnection NetworksWilliam J. Dally. 3 [doi]
- Implementation and Evaluation of a Dynamically Routed Processor Operand NetworkPaul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger. 7-17 [doi]
- On Characterizing Performance of the Cell Broadband Engine Element Interconnect BusThomas William Ainsworth, Timothy Mark Pinkston. 18-29 [doi]
- Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoCDonghyun Kim, Kwanho Kim, Joo-Young Kim, Seung-Jin Lee, Hoi-Jun Yoo. 30-39 [doi]
- Architecture of the Scalable Communications CoreJeffrey D. Hoffman, David Arditti Ilitzky, Anthony Chun, Aliaksei Chapyzhenka. 40-52 [doi]
- On the Design of a Photonic Network-on-ChipAssaf Shacham, Keren Bergman, Luca P. Carloni. 53-64 [doi]
- NoC Communication Strategies Using Time-to-Digital ConversionCrescenzo D Alessandro, Nikolaos Minas, Keith Heron, David Kinniment, Alexandre Yakovlev. 65-74 [doi]
- A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM DesignsShuming Chen, Xiangyuan Liu. 75-82 [doi]
- Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS ArchitecturesIvan Miro Panades, Alain Greiner. 83-94 [doi]
- Transaction-Based Communication-Centric DebugKees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek. 95-106 [doi]
- The Impact of Higher Communication Layers on NoC Supported MP-SoCsThéodore Marescaux, Erik Brockmeyer, Henk Corporaal. 107-116 [doi]
- The Power of Priority: NoC Based Distributed Cache CoherencyEvgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny. 117-126 [doi]
- A Generic Model for Formally Verifying NoC Communication Architectures: A Case StudyDominique Borrione, Amr Helmy, Laurence V. Pierre, Julien Schmaltz. 127-136 [doi]
- Access Regulation to Hot-Modules in Wormhole NoCsIsask har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny. 137-148 [doi]
- Design Technologies for Networks on ChipsGiovanni De Micheli. 149 [doi]
- Approaching Ideal NoC Latency with Pre-Configured RoutesGeorge Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis. 153-162 [doi]
- A Power and Energy Exploration of Network-on-Chip ArchitecturesArnab Banerjee, Robert D. Mullins, Simon W. Moore. 163-172 [doi]
- A Hybrid Analog-Digital Routing Network for NoC Dynamic RoutingTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam. 173-182 [doi]
- Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on ChipsJose Flich, Andres Mejia, Pedro López, José Duato. 183-194 [doi]
- A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global RoutingStephan Bourduas, Zeljko Zilic. 195-204 [doi]
- Towards Open Network-on-Chip BenchmarksCristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu. 205 [doi]
- An Analytical Approach for Dimensioning Mixed Traffic NetworksPer Badlund, Axel Jantsch. 215 [doi]
- Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-ChipXuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach. 216 [doi]
- A Study of NoC Exit StrategiesMikael Millberg, Axel Jantsch. 217 [doi]
- QNoC Asynchronous Router with Dynamic Virtual Channel AllocationRostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon. 218 [doi]
- Reducing Interconnect Cost in NoC through Serialized Asynchronous LinksSimon Ogg, Enrico Valli, Crescenzo D Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini. 219 [doi]
- Thermal Impacts on NoC InterconnectsSheng Xu, Ibis Benito, Wayne P. Burleson. 220 [doi]
- NOC-centric Security of Reconfigurable SoCJean-Philippe Diguet, Samuel Evain, Romain Vaslin, Guy Gogniat, Emmanuel Juin. 223-232 [doi]
- Trade-offs in the Configuration of a Network on Chip for Multiple Use-CasesAndreas Hansson, Kees Goossens. 233-242 [doi]
- Mesh of Tree: Unifying Mesh and MFPGA for Better Device PerformancesZied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez. 243-252 [doi]
- NoC-Based FPGA: Architecture and RoutingRoman Gindin, Israel Cidon, Idit Keidar. 253-264 [doi]
- Reflections on 10 Years as a Commercial On-Chip Interconnect ProviderDrew Wingard. 265 [doi]
- NoC: Network or Chip?Israel Cidon. 269 [doi]
- NoC Design and Implementation in 65nm TechnologyAntonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini. 273-282 [doi]
- Implications of Rent s Rule for NoC Design and Its Fault-ToleranceDaniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore. 283-294 [doi]
- ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoCCedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet. 295-306 [doi]
- Implementing DSP Algorithms with On-Chip NetworksXiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud. 307-316 [doi]
- A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip NetworkWein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, An-Yeu Wu. 317-322 [doi]
- Fast, Accurate and Detailed NoC SimulationsPascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit. 323-332 [doi]