Abstract is missing.
- Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systemsPamela Wattebled, Jean-Philippe Diguet, Jean-Luc Dekeyser. 1-8 [doi]
- Automatic run-time manager generation for reconfigurable MPSoC architecturesGianluca Durelli, Christian Pilato, Andrea Cazzaniga, Donatella Sciuto, Marco D. Santambrogio. 1-8 [doi]
- A framework for self-reconfigurable DCTs based on multiobjective optimization of the Power-Performance-Accuracy spaceDaniel Llamocca, Marios S. Pattichis, Cesar Carranza. 1-6 [doi]
- Distributed control for reconfigurable FPGA systems: A high-level design approachChiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser. 1-8 [doi]
- Hardware implementation of GMDH-type artificial neural networks and its use to predict approximate three-dimensional structures of proteinsAndré L. S. Braga, Janier Arias-Garcia, Carlos H. Llanos, Márcio Dorn, Alfredo Foltran, Leandro dos Santos Coelho. 1-8 [doi]
- Adaptive parallelism exploitation under physical and real-time constraints for resilient systemsFábio P. Itturriet, Gabriel L. Nazar, Ronaldo Rodrigues Ferreira, Álvaro F. Moreira, Luigi Carro. 1-8 [doi]
- Smart technologies for effective reconfiguration: The FASTER approachMarco D. Santambrogio, Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Christian Pilato, Georgi Gaydadjiev, Dirk Stroobandt, Tom Davidson, Tobias Becker, Tim Todman, Wayne Luk, Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Donatella Sciuto. 1-7 [doi]
- On implementability of Polymorphic Register FilesCatalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev. 1-6 [doi]
- Transport layer aware design of network interface in many-core systemsMohammad Fattah, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila. 1-7 [doi]
- Hardware acceleration of combined cipher and forward error correction for low-power wireless applicationsFrançois Philipp, Conrad Klytta, Manfred Glesner, Elvio Dutra. 1-7 [doi]
- Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environmentsDimitris Bekiaris, Efstathios Sotiriou-Xanthopoulos, George Economakos, Dimitrios Soudris. 1-8 [doi]
- Power management techniques in an FPGA-based WSN node for high performance applicationsMiguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo. 1-8 [doi]
- High-level model of sensor architecture for hardware and software design space explorationNicolas Serna, François Verdier. 1-8 [doi]
- Designing formal reconfiguration control using UML/MARTESébastien Guillet, Florent de Lamotte, Nicolas Le Griguer, Éric Rutten, Guy Gogniat, Jean-Philippe Diguet. 1-8 [doi]
- Invited paper: On-chip monitoring for adaptive heterogeneous multicore systemsDiana Göhringer, Mounir Chemaou, Michael Hübner. 1-7 [doi]
- Fast integration of hardware accelerators for dynamically reconfigurable architectureClement Foucher, Fabrice Muller, Alain Giulieri. 1-7 [doi]
- Exploiting FPGA-aware merging of custom instructions for runtime reconfigurationSiew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke. 1-8 [doi]
- Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based systemPascal Cotret, Florian Devic, Guy Gogniat, Benoît Badrignans, Lionel Torres. 1-8 [doi]
- Translating Java for resource constrained embedded systemsGary Plumbridge, Neil C. Audsley. 1-8 [doi]
- Using genetic algorithms to map hard real-time on NoC-based systemsAdrian Racu, Leandro Soares Indrusiak. 1-8 [doi]
- RIVER architecture: Reconfigurable flow and fabric for parallel stream processing on FPGAsDominic Hillenbrand, Christian Brugger, Jie Tao, Shufan Yang, Matthias Balzer. 1-8 [doi]
- Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraintsMohsin Amin, Mihkel Tagel, Gert Jervan, Thomas Hollstein. 1-6 [doi]
- Dynamically reconfigurable flux limiter functions in MUSCL schemeMohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. 1-7 [doi]
- Fault-tolerant network interface for spatial division multiplexing based Network-on-ChipAnup Das, Akash Kumar, Bharadwaj Veeravalli. 1-8 [doi]
- GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networksMasoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila. 1-5 [doi]
- Energy and power estimation of Coarse-Grain Reconfigurable Array based Fast Fourier Transform acceleratorsWaqar Hussain, Tapani Ahonen, Roberto Airoldi, Jari Nurmi. 1-4 [doi]
- A MARTE subset to enable application-platform co-simulation and schedulability analysis of NoC-based embedded systemsLeandro Soares Indrusiak, Imran Rafiq Quadri, Ian Gray, Neil C. Audsley, Andrey Sadovykh. 1-7 [doi]
- Fast spiking neural network architecture for low-cost FPGA devicesTaras Iakymchuk, Alfredo Rosado, José V. Francés, Manuel Batallre. 1-6 [doi]
- A solution to the data re-ordering problem for multi-pipeline streaming applications on clustered MPSoCDaniela Genius, Khouloud Zine el Abidine. 1-8 [doi]
- Embedded UML design flow to the configurable LE1 MultiCore VLIW processorMark Milward, David Stevens, Vassilios Chouliaras. 1-8 [doi]
- Accuracy evaluation of GEM5 simulator systemAnastasiia Butko, Rafael Garibotti, Luciano Ost, Gilles Sassatelli. 1-7 [doi]
- A RTRM proposal for multi/many-core platforms and reconfigurable applicationsPatrick Bellasi, Giuseppe Massari, William Fornaciari. 1-8 [doi]
- Programming strategies for runtime adaptabilityJoão M. P. Cardoso. 1-8 [doi]
- A flexible approach for compiling scilab to reconfigurable multi-core embedded systemsTimo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Menard, Olivier Sentieys, Diana Göhringer, Thomas Perschke. 1-8 [doi]
- MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAsRenaud Van Langendonck, Angelo Kuti Lusala, Jean-Didier Legat. 1-8 [doi]
- A heterogeneous modules interconnection architecture for FPGA-based partial dynamic reconfigurationMiao He, Yanzhe Cui, Mohammad H. Mahoor, Richard M. Voyles. 1-7 [doi]
- Invited paper: Acceleration of computationally-intensive kernels in the reconfigurable eraKyprianos Papadimitriou, Charalampos Vatsolakis, Dionisios N. Pnevmatikatos. 1-5 [doi]
- Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-ChipHaoyuan Ying, Thomas Hollstein, Klaus Hofmann. 1-6 [doi]
- Partially reconfigurable TVWS transceiver for use in UK and US marketsRoss A. Elliot, Martin A. Enderwitz, Ke He, Faisal Darbari, Louise Crockett, Stephan Weiss, Robert W. Stewart. 1-6 [doi]
- ENOSYS FP7 EU project: An integrated modeling and synthesis flow for embedded systems designEtienne Brosse, Imran Rafiq Quadri, Andrey Sadovykh, Frank Ieromnimon, Dimitrios Kritharidis, Rafael Catrou, Michel Sarlotte. 1-5 [doi]
- MADES FP7 EU project: Effective high level SysML/MARTE methodology for real-time and embedded avionics systemsImran Rafiq Quadri, Etienne Brosse, Ian Gray, Nikolas Drivalos Matragkas, Leandro Soares Indrusiak, Matteo Rossi, Alessandra Bagnato, Andrey Sadovykh. 1-8 [doi]