Akinori Kanasugi - researchr alias

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Viewing Publication 1 - 21 from 21

2020

A design of EPIC type processor based on MIPS architectureTakahito Hayashi, Akinori Kanasugi. alr, 25(1):59-63, 2020. [doi]

An integrated machine code monitor for a RISC-V processor on an FPGAHiroaki Kaneko, Akinori Kanasugi. alr, 25(3):427-433, 2020. [doi]

2018

Design of Approximate Arithmetic Circuits within ToleranceAkihiko Tsukahara, Akinori Kanasugi. ceec 2018: 79-82 [doi]

2015

Hardware implementation of evolutionary algorithms using dynamic reconfiguration technologyAkinori Kanasugi, Akihiko Tsukahara, Ki Ando. nc, 14(4):593-601, 2015. [doi]

Generator of dynamically reconfigurable processorTakahiko Sega, Akinori Kanasugi, Ki Ando. alr, 20(2):103-108, 2015. [doi]

Design of a Real Coded GA ProcessorAkihiko Tsukahara, Akinori Kanasugi. ijcci 2015: 334-339 [doi]

2014

2012

A Processor for GA based on Redundant Binary Number using FPGAAkira Murayama, Akinori Kanasugi. jnit, 3(3):1-9, 2012. [doi]

2010

2007

Design and Implementation of Rough Rules Generation from Logical Rules on FPGA BoardAkinori Kanasugi, Mitsuhiro Matsumoto. rseisp 2007: 594-602 [doi]

A Processor for Genetic Algorithm using Dynamically Reconfigurable MemoryAkinori Kanasugi, Akihiko Tsukahara. jcit, 2(1):4-15, 2007. [doi]

Genetic Algorithm that can Dynamically Change Number of Individuals and AccuracyAkihiko Tsukahara, Akinori Kanasugi. fbit 2007: 785-789 [doi]

2001

A Design of Architecture for Rough Set ProcessorAkinori Kanasugi. jsai 2001: 406-412 [doi]

1998

A Genetic Algorithm for Switchbox Routing ProblemAkinori Kanasugi, Takashi Shimayama, Naoshi Nakaya, Takeshi Iizuka. rsctc 1998: 247-254 [doi]

1997

A digital application of chaotic oscillation modes in Josephson circuitMititada Morisue, Masayuki Yamadaya, Hiroshi Noguchi, Akinori Kanasugi. ijis, 12(4):267-290, 1997. [doi]

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