Chia-Lung Hung - researchr alias

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Viewing Publication 1 - 4 from 4

2011

Efficient pipelined architecture for competitive learningHui-Ya Li, Chia-Lung Hung, Wen-Jyi Hwang, Yi-Tsan Hung. jpdc, 71(2):236-244, 2011. [doi]

2010

Hardware Implementation of k-Winner-Take-All Neural Network with On-chip LearningHui-Ya Li, Chien-Min Ou, Yi-Tsan Hung, Wen-Jyi Hwang, Chia-Lung Hung. cse 2010: 340-345 [doi]

An Efficient Pipelined Architecture for Fast Competitive LearningHui-Ya Li, Chia-Lung Hung, Wen-Jyi Hwang. ica3pp 2010: 381-390 [doi]

2009

Efficient K-Means VLSI Architecture for Vector QuantizationHui-Ya Li, Wen-Jyi Hwang, Chih-Chieh Hsu, Chia-Lung Hung. scia 2009: 440-449 [doi]

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