Rie Soejima - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 5 from 5

2017

HLS-Based FPGA Acceleration of Building-Cube Stencil ComputationRie Soejima, Yuichiro Shibata, Kiyoshi Oguri. cisis 2018: 463-474 [doi]

Comparative Evaluation of FPGA Implementation Alternatives for Real-Time Robust Ellipse Estimation based on RANSAC AlgorithmTheint Theint Thu, Jimpei Hamamura, Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri. ieicet, 100-A(7):1409-1417, 2017. [doi]

2015

Performance Modeling of Stencil Computing on a Stream-Based FPGA Accelerator for Efficient Design Space ExplorationKeisuke Dohi, Koji Okina, Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri. ieicet, 98-D(2):298-308, 2015. [doi]

Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline OptimizationKoji Okina, Rie Soejima, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri. sigarch, 43(4):9-14, 2015. [doi]

2014

A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level SynthesisRie Soejima, Koji Okina, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri. sigarch, 42(4):69-74, 2014. [doi]

Sign in or sign up to see more results.

runs on WebDSL