Journal: Computer Architecture Letters

Volume 10, Issue 2

29 -- 32Jason Mars, Lingjia Tang, Robert Hundt. Heterogeneity in "Homogeneous" Warehouse-Scale Computers: A Performance Opportunity
33 -- 36George Michelogiannakis, Nan Jiang, Daniel U. Becker, William J. Dally. Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks
37 -- 40Chen-Han Ho, Garret Staus, Aaron Ullmer, Karu Sakaralingam. Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities
41 -- 44Carles Hernández, Antoni Roca, Jose Flich, Federico Silla, José Duato. Fault-Tolerant Vertical Link Design for Effective 3D Stacking
45 -- 48Inseok Choi, Minshu Zhao, Xu Yang, Donald Yeung. Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor
49 -- 52Pablo Prieto, Valentin Puente, José-Ángel Gregorio. Multilevel Cache Modeling for Chip-Multiprocessor Systems
53 -- 56Kostas Siozios, Dimitrios Rodopoulos, Dimitrios Soudris. On Supporting Rapid Thermal Analysis

Volume 10, Issue 1

1 -- 3Kevin Skadron. Editorial: Letter from the Editor-in-Chief
4 -- 7Hans Vandierendonck, André Seznec. Fairness Metrics for Multi-Threaded Processors
8 -- 11Jie Tang, Shaoshan Liu, Zhimin Gu, Chen Liu, Jean-Luc Gaudiot. Prefetching in Embedded Mobile Systems Can Be Energy-Efficient
12 -- 15Omer Khan, Mieszko Lis, Yildiz Sinangil, Srinivas Devadas. DCC: A Dependable Cache Coherence Multicore Architecture
16 -- 19Paul Rosenfeld, Elliott Cooper-Balis, Bruce Jacob. DRAMSim2: A Cycle Accurate Memory System Simulator
20 -- 23Chunyang Gou, Georgi Gaydadjiev. Exploiting SPMD Horizontal Locality
24 -- 27Xiaoqun Wang, Zhen Ji, Chen Fu, Ming Hu. GCMS: A Global Contention Management Scheme in Hardware Transactional Memory