| 33 | -- | 36 | Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, Jinwoo Shin. DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function |
| 37 | -- | 40 | Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Xiaowen Chen, Hu Chen, Haibo Wang. Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures |
| 41 | -- | 44 | Reena Panda, Paul V. Gratz, Daniel A. Jimenez. B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors |
| 45 | -- | 48 | Timothy N. Miller, Renji Thomas, Radu Teodorescu. Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units |
| 49 | -- | 52 | Yang Li, Rami G. Melhem, Alex K. Jones. Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors |
| 53 | -- | 56 | Christina Delimitrou, Sriram Sankar, Kushagra Vaid, Christos Kozyrakis. Decoupling Datacenter Storage Studies from Access to Large-Scale Applications |
| 57 | -- | 60 | Jie Chen 0020, Guru Venkataramani, Gabriel Parmer. The Need for Power Debugging in the Multi-Core Environment |
| 61 | -- | 64 | Justin Meza, Jichuan Chang, Hanbin Yoon, Onur Mutlu, Parthasarathy Ranganathan. Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management |
| 65 | -- | 68 | Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser. MultiAmdahl: How Should I Divide My Heterogenous Chip? |