| 37 | -- | 38 | Jose F. Martinez. Editorial |
| 39 | -- | 42 | Xun Jian, John Sartori, Henry Duwe, Rakesh Kumar 0002. High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity |
| 43 | -- | 46 | Rakan Maddah, Sangyeun Cho, Rami G. Melhem. Data Dependent Sparing to Manage Better-Than-Bad Blocks |
| 47 | -- | 50 | Hanjoon Kim, Yonggon Kim, John Kim. Clumsy Flow Control for High-Throughput Bufferless On-Chip Networks |
| 51 | -- | 54 | Yi Kai, Yi Wang 0004, Bin Liu. GreenRouter: Reducing Power by Innovating Router's Architecture |
| 55 | -- | 58 | Yongsoo Joo, Sangsoo Park. A Hybrid PRAM and STT-RAM Cache Architecture for Extending the Lifetime of PRAM Caches |
| 59 | -- | 62 | Emily R. Blem, Hadi Esmaeilzadeh, Renée St. Amant, Karthikeyan Sankaralingam, Doug Burger. Multicore Model from Abstract Single Core Inputs |
| 63 | -- | 66 | Pierre Michaud. Demystifying multicore throughput metrics |
| 67 | -- | 70 | Priyanka Tembey, Augusto Vega, Alper Buyuktosunoglu, Dilma Da Silva, Pradip Bose. SMT Switch: Software Mechanisms for Power Shifting |