| 1 | -- | 4 | Angelos Arelakis, Per Stenström. A Case for a Value-Aware Cache |
| 5 | -- | 8 | Zheng Chen, Huaxi Gu, Yintang Yang, Luying Bai, Hui Li. A Power Efficient and Compact Optical Interconnect for Network-on-Chip |
| 9 | -- | 12 | Emilio G. Cota, Paolo Mantovani, Michele Petracca, Mario R. Casu, Luca P. Carloni. Accelerator Memory Reuse in the Dark Silicon Era |
| 13 | -- | 16 | Yu-Liang Chou, Shaoshan Liu, Eui-Young Chung, Jean-Luc Gaudiot. An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC |
| 17 | -- | 20 | Nadav Rotem, Yosi Ben-Asher. Block Unification IF-conversion for High Performance Architectures |
| 21 | -- | 24 | Aleksandar Ilic, Frederico Pratas, Leonel Sousa. Cache-aware Roofline model: Upgrading the loft |
| 25 | -- | 28 | Efraim Rotem, Ran Ginosar, Uri C. Weiser, Avi Mendelson. Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management |
| 29 | -- | 32 | Yaman Cakmakci, Oguz Ergin. Exploiting Virtual Addressing for Increasing Reliability |
| 33 | -- | 36 | Yuhao Zhu, Aditya Srikanth, Jingwen Leng, Vijay Janapa Reddi. Exploiting Webpage Characteristics for Energy-Efficient Mobile Web Browsing |
| 37 | -- | 40 | Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser. Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC |
| 41 | -- | 44 | Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser. Memristor-Based Multithreading |
| 45 | -- | 48 | Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain. Optimization of Application-Specific Memories |
| 49 | -- | 52 | Yunlong Xu, Rui Wang, Nilanjan Goswami, Tao Li, Depei Qian. Software Transactional Memory for GPU Architectures |
| 53 | -- | 56 | Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas. Thread Migration Prediction for Distributed Shared Caches |