Journal: Computer Architecture Letters

Volume 15, Issue 2

69 -- 72Shuang Liang, Shouyi Yin, Leibo Liu, Yike Guo, Shaojun Wei. A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration
73 -- 76Bo-Cheng Charles Lai, Luis Garrido Platero, Hsien-Kai Kuo. A Quantitative Method to Data Reuse Patterns of SIMT Applications
77 -- 80Yaman Cakmaki, Will Toms, Javier Navaridas, Mikel Luján. Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling
81 -- 84Erik Tomusk, Christophe Dubach. Diversity: A Design Goal for Heterogeneous Processors
85 -- 88Milad Hashemi, Debbie Marr, Doug Carmean, Yale N. Patt. Efficient Execution of Bursty Applications
89 -- 92Sudarsun Kannan, Moinudin Qureshi, Ada Gavrilovska, Karsten Schwan. Energy Aware Persistence: Reducing the Energy Overheads of Persistent Memory
93 -- 96Alejandro Valero, Negar Miralaei, Salvador Petit, Julio Sahuquillo, Timothy M. Jones. Enhancing the L1 Data Cache Design to Mitigate HCI
97 -- 100Rathijit Sen, David A. Wood. GPGPU Footprint Models to Estimate per-Core Power
101 -- 104Daejin Jung, Sheng Li, Jung Ho Ahn. Large Pages on Steroids: Small Ideas to Accelerate Big Memory Applications
105 -- 108Javier Verdú, Alex Pajuelo. Performance Scalability Analysis of JavaScript Applications with Web Workers
109 -- 112Christina Delimitrou, Christos Kozyrakis. Security Implications of Data Mining in Cloud Scheduling
113 -- 116Zhenning Wang, Jun Yang, Rami G. Melhem, Bruce R. Childers, Youtao Zhang, Minyi Guo. Simultaneous Multikernel: Fine-Grained Sharing of GPUs
117 -- 120Chulian Zhang, Hamed Tabkhi, Gunar Schirner. Studying Inter-Warp Divergence Aware Execution on GPUs
121 -- 124Arash Tavakkol, Pooyan Mehrvarzy, Hamid Sarbazi-Azad. TBM: Twin Block Management Policy to Enhance the Utilization of Plane-Level Parallelism in SSDs
125 -- 128Bruce Jacob. The 2 PetaFLOP, 3 Petabyte, 9 TB/s, 90 kW Cabinet: A System Architecture for Exascale and Big Data
129 -- 132He Xiao, Wen Yueh, Saibal Mukhopadhyay, Sudhakar Yalamanchili. Thermally Adaptive Cache Access Mechanisms for 3D Many-Core Architectures
133 -- 136Qi Hu, Peng Liu, Michael C. Huang. Threads and Data Mapping: Affinity Analysis for Traffic Reduction

Volume 15, Issue 1

1 -- 4Wo-Tak Wu, Ahmed Louri. A Methodology for Cognitive NoC Design
5 -- 8Seyyed Hossein Seyyedaghaei Rezaei, Abbas Mazloumi, Mehdi Modarressi, Pejman Lotfi-Kamran. Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip
9 -- 12Miguel Gorgues, Jose Flich. End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance
13 -- 16Biswabandan Panda, Shankar Balachandran. Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers
17 -- 20Abdulaziz Eker, Oguz Ergin. Exploiting Existing Copies in Register File for Soft Error Correction
21 -- 24Matthew Maycock, Simha Sethumadhavan. Hardware Enforced Statistical Privacy
25 -- 28Dongdong Li, Tor M. Aamodt. Inter-Core Locality Aware Memory Scheduling
29 -- 32Libei Pu, Kshitij Doshi, Ellis Giles, Peter J. Varman. Non-Intrusive Persistence with a Backend NVM Controller
33 -- 36Paulo Garcia, Tiago Gomes, João L. Monteiro, Adriano Tavares, Mongkol Ekpanyapong. On-Chip Message Passing Sub-System for Embedded Inter-Domain Communication
37 -- 40Minghua Li, Guancheng Chen, Qijun Wang, Yonghua Lin, Peter Hofstee, Per Stenström, Dian Zhou. PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor
41 -- 44Mohammad Alian, Daehoon Kim, Nam Sung Kim. pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems
45 -- 49Yoongu Kim, Weikun Yang, Onur Mutlu. Ramulator: A Fast and Extensible DRAM Simulator
50 -- 53Lena E. Olson, Simha Sethumadhavan, Mark D. Hill. Security Implications of Third-Party Accelerators
54 -- 57Bruce Jacob. The Case for VLIW-CMP as a Building Block for Exascale
58 -- 61Marios Kleanthous, Yiannakis Sazeides, Emre Özer, Chrysostomos Nicopoulos, Panagiota Nikolaou, Zacharias Hadjilambrou. Toward Multi-Layer Holistic Evaluation of System Designs
62 -- 65Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan. Towards High-Performance Bufferless NoCs with SCEPTER