| 2 | -- | 5 | Chuanjun Zhang. Balanced instruction cache: reducing conflict misses of direct-mapped caches through balanced subarray accesses |
| 6 | -- | 9 | Guilherme Ottoni, Ram Rangan, Adam Stoler, Matthew J. Bridges, David I. August. From sequential programs to concurrent threads |
| 10 | -- | 13 | Amit K. Gupta, William J. Dally. Topology optimization of interconnection networks |
| 14 | -- | 17 | T. Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé. Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors |
| 18 | -- | 21 | Nicholas Riley, Craig B. Zilles. Probabilistic counter updates for predictor hysteresis and bias |
| 22 | -- | 25 | Huiyang Zhou. A case for fault tolerance and performance enhancement using chip multi-processors |
| 26 | -- | 29 | Moon-Sang Lee, Sang-Kwon Lee, Joonwon Lee, Seung Ryoul Maeng. Adopting system call based address translation into user-level communication |
| 30 | -- | 33 | Jung Ho Ahn, William J. Dally. Data parallel address architecture |
| 34 | -- | 37 | Noel Eisley, Li-Shiuan Peh, Li Shang. In-network cache coherence |
| 38 | -- | 41 | Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck. Performance modeling using Monte Carlo simulation |