| 430 | -- | 0 | Minoru Fujishima. Foreword |
| 431 | -- | 439 | Jung Nam Bae, Saichandrateja Radhapuram, Ikkyun Jo, Weimin Wang, Takao Kihara, Toshimasa Matsuoka. A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices |
| 440 | -- | 443 | Pil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang. An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis |
| 444 | -- | 451 | Hirofumi Takishita, Shuhei Tanakamaru, Sheyang Ning, Ken Takeuchi. Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths |
| 452 | -- | 457 | Luis Fortino Cisneros Sinencio, Alejandro Díaz-Sánchez, Jaime Ramírez-Angulo. A Noise-Robust Positive-Feedback Floating-Gate Logic |
| 458 | -- | 465 | Kaoru Kohira, Hiroki Ishikuro. A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link |
| 466 | -- | 473 | Katsuhiro Tsuji, Kazuo Terada, Ryo Takeda, Hisato Fujisaka. Study on Threshold Voltage Variation Evaluated by Charge-Based Capacitance Measurement |
| 474 | -- | 480 | Akira Heya, Naoto Matsuo, Kazuhiro Kanda. Low-Temperature Activation in Boron Ion-Implanted Silicon by Soft X-Ray Irradiation |
| 481 | -- | 490 | Chia-Wen Chang, Kai-Yu Lo, Hossameldin A. Ibrahim, Ming-Chiuan Su, Yuan-Hua Chu, Shyh-Jye Jou. A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques |
| 491 | -- | 502 | Yuta Suzuki, Kota Sata, Junichi Kako, Kohei Yamaguchi, Fumio Arakawa, Masato Edahiro. Parallel Design of Feedback Control Systems Utilizing Dead Time for Embedded Multicore Processors |