| 319 | -- | 327 | Nijwm Wary, Pradip Mandal. High-speed energy-efficient bi-directional transceiver for on-chip global interconnects |
| 328 | -- | 335 | Jens Spinner, Jürgen Freudenberger. Decoder architecture for generalised concatenated codes |
| 336 | -- | 342 | Jeng-Shyang Pan, Chiou-Yng Lee, Yao Li. m) based on Dickson-Karatsuba decomposition |
| 343 | -- | 352 | Masoomeh Jasemi, Reza Faghih Mirzaee, Keivan Navi, Nader Bagherzadeh. Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic |
| 353 | -- | 361 | Mury Thian, Vincent F. Fusco. Holistic design strategy for high-selectivity low-loss integrated millimetre-wave image-reject filters |
| 362 | -- | 369 | Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine. Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design |
| 370 | -- | 376 | Asma Dehghani, Mohsen Saneei, Ali Mahani. Time-to-digital convertor based on resolution control |
| 377 | -- | 383 | Kota Naga Srinivasarao Batta, Indrajit Chakrabarti, Mohammad Nawaz Ahmad. High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter |