| 14 | -- | 0 | Saraju P. Mohanty. Special section on new circuit and architecture-level solutions for multidiscipline systems |
| 15 | -- | 0 | Ashok Srivastava, Yao Xu, Yang Liu, Ashwani K. Sharma, Clay Mayberry. CMOS LC voltage controlled oscillator design using multiwalled and single-walled carbon nanotube wire inductors |
| 16 | -- | 0 | Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.. Dynamic clock stretching for variation compensation in VLSI circuit design |
| 17 | -- | 0 | Sudip Roy, Debasis Mitra, Bhargab B. Bhattacharya, Krishnendu Chakrabarty. Congestion-aware layout design for high-throughput digital microfluidic biochips |
| 18 | -- | 0 | Narayanan M. Komerath, Aravinda Kar. Retail beamed power using millimeter waves: Survey |
| 19 | -- | 0 | Ashok Kumar Palaniswamy, Spyros Tragoudas. An efficient heuristic to identify threshold logic functions |
| 20 | -- | 0 | Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli. Effect of process variations in 3D global clock distribution networks |
| 21 | -- | 0 | Eren Kursun, Jamil A. Wakil, Mukta Farooq, Robert Hannon. Spatial and temporal thermal characterization of stacked multicore architectures |
| 22 | -- | 0 | Bao Liu, Xuemei Chen, Fiona Teshome. Resilient and adaptive performance logic |
| 23 | -- | 0 | Kevin Chang, Sujay Deb, Amlan Ganguly, Xinmin Yu, Suman Prasad Sah, Partha Pratim Pande, Benjamin Belzer, Deuk Hyoun Heo. Performance evaluation and design trade-offs for wireless network-on-chip architectures |
| 24 | -- | 0 | Byung-Soo Choi, Rodney Van Meter. A Θ( √ n)-depth quantum adder on the 2D NTC quantum computer architecture |
| 25 | -- | 0 | Jiale Huang, Minhao Zhu, Shengqi Yang, Pallav Gupta, Wei Zhang 0012, Steven M. Rubin, Gilda Garretón, Jin He. A physical design tool for carbon nanotube field-effect transistor circuits |