| 3 | -- | 7 | Krzysztof Goczyla. A microcomputer database design |
| 9 | -- | 14 | S. M. Kuo Pan, Yukio Kaneda. A table oriented database-prolog system |
| 15 | -- | 20 | Prem Malhotra, Rudolph E. Seviora. Knowledge bases for digital circuit understanding |
| 21 | -- | 26 | S. Grünwald. The selection of expert system development environments |
| 27 | -- | 32 | P. Grimaldi, A. Marcelli. Toward a structured approach to expert system development |
| 33 | -- | 38 | Naphtali Rishe, Doron Tal, Qiang Li. Architecture for a massively parallel database machine |
| 41 | -- | 46 | L. de Sá, J. Dias, V. Silva. Image processing system with multiple DSPs |
| 47 | -- | 50 | M. Vlajnic, A. Purkovic, Z. Mladenovic, S. Nedic. Universal DSP board |
| 51 | -- | 54 | H. Bohr. Supercomputer accelerator card for PC |
| 55 | -- | 60 | Jürgen Kreyßig, Horst Schukat, Hans Christoph Zeidler, Hans Diel, Helmut Weber. An intelligent disk controller - A processor system for file management and querry functions |
| 61 | -- | 64 | K. Bruck, M. Griese, Ch. Jatho, A. S. Kirilov, V. I. Prikhodko. Some computer graphics algorithms and their hardware realization |
| 65 | -- | 69 | Ludo Cuypers. Computer music programming |
| 71 | -- | 75 | Wolfgang A. Halang. Education of real-time systems engineers |
| 79 | -- | 83 | P. Pardo, Yair Be'ery. SPL - A different high level language for systolic processors |
| 85 | -- | 90 | Fabrizio Lombardi, Donatella Sciuto. Linear testability conditions for two-dimensional arrays |
| 91 | -- | 96 | D. Tal, István Erényi, John Craig Comfort. A fault-tolerant systolic data flow machine |
| 97 | -- | 105 | G. L. Aranci, C. A. Binda, U. Clerici, E. Comignaghi. A fault tolerant oriented CMOS systolic implementation of an FIR filter |
| 107 | -- | 112 | J. Tasic, R. Sega. Systolic arrays in adaptive digital filters |
| 113 | -- | 118 | V. N. Doniants, V. G. Lazarev, R. Stefanelli. Fault-tolerance of cellular processing arrays: Algorithmic methods for yield enhancement and reliability |
| 121 | -- | 125 | Norbert Drescher. A new microarchitecture based on a RISC like structure but with a CISC like instruction set |
| 127 | -- | 132 | Antonio Núñez, Roberto Sarmiento, Pedro P. Carballo. Some results in GaAs processor design using LSI integrated circuits |
| 133 | -- | 138 | Patrick Abellard, B. Barbagelata. A data flow numerical processing operator |
| 139 | -- | 142 | Piotr Krzyzagórski. Avoiding deadlock with a dual-port memory |
| 143 | -- | 148 | V. Olman, R. Raud, A. Lepp. Probability based timing verification |
| 151 | -- | 155 | Gyula Csopaki. Hardware description language for specification of digital systems |
| 157 | -- | 162 | T. Grabowiecki, Adam Pawlak. PROLOG as a formalism for VLSI design specification |
| 163 | -- | 170 | Nikolaos G. Bourbakis, I. N. Savvides. Geometric transformations for optimum VLSI layout placement |
| 171 | -- | 176 | B. Hoppe. Circuit optimization: Gate level modelling and multiobjective programming |
| 177 | -- | 182 | Mustahsan Mir, M. H. Imam. Optimal placement for hierarchical VLSI layout design |
| 183 | -- | 187 | S. Gai, Antonio Lioy. A multilevel hardware description language |
| 189 | -- | 194 | Lambert Spaanenburg. Design of a 1-chip IBM-3270 protocol handler |
| 197 | -- | 201 | J. J. Narraway. Probability machines |
| 203 | -- | 208 | Borko Furht. A contribution to classification and evaluation of structures for parallel computers |
| 209 | -- | 212 | Eberhard Zehendner, Theo Ungerer. A simulation method for parallel computer architectures |
| 213 | -- | 219 | Mike P. Papazoglou, Adam Pawlak, Wlodzimierz Wrona. Multiprocessor modelling: An example of object-oriented development |
| 221 | -- | 227 | L. Tassakos, Klaus W. Plessmann. pdvPool: A real-time object-oriented multiprocessor system |
| 229 | -- | 232 | Edil Severiano Tavares Fernandes, C. L. de Amorim, Valmir C. Barbosa, Felipe M. G. Franca, A. F. de Souza. MPH - A Hybrid Parallel Machine |
| 233 | -- | 238 | D. C. Shin, S. C. Moon. A concurrency control scheme for nested transactions |
| 239 | -- | 243 | B. De Decker, Pierre Verbaeten. Modeling distributed systems: Communication issues in Hermix |
| 247 | -- | 251 | N. Stanley Scott, Danny Crookes, Peter Milligan, P. L. Kilpatrick, Philip J. Morrow. A case study in improving programming productivity on transputer networks |
| 253 | -- | 257 | H. Zedan, R. F. Stone, D. S. Simpson. PCHAN: A notion for dynamic resource management in distributed occam systems |
| 259 | -- | 263 | Ermanno Di Zitti, Giacomo M. Bisio, Francesco Curatelli, Giancarlo Parodi. High efficiency solution of triangular system equations on a 2-D array of transputers |
| 265 | -- | 270 | Adriano Valenzano, Paolo Montuschi, Luigi Ciminiera. Implementation of algorithms for graphic surface modeling using transputers |
| 271 | -- | 276 | Alan Purvis, Ron W. Berry, Peter D. Manning. A multi-transputer based audio computer with MIDI and analogue interfaces |
| 277 | -- | 280 | Hermann Schomberg. Image processing on a transputer-based perfect shuffle machine |
| 281 | -- | 285 | T. J. Jackson, D. J. Mapps, Emmanuel C. Ifeachor, T. Donnelly. A real-time transputer-based system for a digital recording data channel |
| 287 | -- | 292 | E. Binaghi, Giacomo R. Sechi, Roberto Vaccaro, Lorenzo Verdoscia. HCRC-Parallel computer: A massively parallel combined architecture supercomputer |
| 295 | -- | 300 | Joshua Etkin. The transition from network operating systems to distributed global operating systems: Do we stretch too much the real-time requirements? |
| 301 | -- | 306 | M. Ortega, José M. Troya. Live nodes distribution in parallel branch and bound algorithms |
| 307 | -- | 312 | Joshua Etkin, John A. Zinky. Distributed debugging: Network analysis tools |
| 313 | -- | 317 | Iztok Tvrdy. Formal modelling of telematic services using LOTOS |
| 319 | -- | 322 | Rumen Stainov, Ljudmil Manasiev. A distributed communication service |
| 323 | -- | 326 | K.-J. Schulz. Design and implementation of a portable communication transport system for unix network applications in C++ |
| 327 | -- | 331 | S. J. Nichols, R. T. Clarke, P. Mars. Design of a high speed simulation tool for WAN using parallel processing |
| 335 | -- | 339 | E. Carminati, A. Gandelli. A parallel processor for the dynamic characterization of A/D converters |
| 341 | -- | 346 | Nikolaos G. Bourbakis, Mike P. Papazoglou, S. H. Nguyen. Design and simulation using Petri-Nets of a parallel WHT multiprocessor system |
| 347 | -- | 351 | S. Vranes. A heuristic algorithm for real-time application allocation to multimicrocomputer |
| 353 | -- | 358 | R. Trobec, L. Gyergyek, J. Korenini. Two-dimensional parallel system diagnostic |
| 361 | -- | 365 | R. Adamov. A naive approach to software structure validation |
| 367 | -- | 373 | Monica Alderighi, A. Conni, Lauro Mantoani, Giacomo R. Sechi. An automatic software generator in the design of reliable procedural programs |
| 375 | -- | 380 | Tatjana Welzer, Ivan Rozman, József Györkös. Automated normalization tool |
| 381 | -- | 386 | Nelson Q. Vasconcelos, Edil S. T. Fernandes. An environment for concurrent programming in Pascal |
| 387 | -- | 390 | A. Bissett, J. Forrest. An external data structure tool for pascal |