Journal: IEEE Micro

Volume 30, Issue 5

2 -- 4Mateo Valero, Nacho Navarro. Multicore: The View from Europe
5 -- 15Veerle Desmet, Sylvain Girbal, Alex Ramírez, Olivier Temam, Augusto Vega. ArchExplorer for Automatic Design Space Exploration
16 -- 29Alex Ramírez, Felipe Cabarcas, Ben H. H. Juurlink, Mauricio Alvarez, Friman Sánchez, Arnaldo Azevedo, Cor Meenderinck, Catalin Bogdan Ciobanu, Sebastian Isaza, Georgi Gaydadjiev. The SARC Architecture
30 -- 41Manolis Katevenis, Vassilis Papaefstathiou, Stamatis G. Kavadias, Dionisios N. Pnevmatikatos, Federico Silla, Dimitrios S. Nikolopoulos. Explicit Communication and Synchronization in SARC
54 -- 65Stefanos Kaxiras, Georgios Keramidas. SARC Coherence: Scaling Directory Cache Coherence in Performance and Power
66 -- 75Theo Ungerer, Francisco J. Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quiñones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Cassé, Sascha Uhrig, Irakli Guliashvili, Michael Houston, Florian Kluge, Stefan Metzlaff, Jörg Mische. Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability
76 -- 87Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Riviere, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel. The Velox Transactional Memory Stack
88 -- 97Koen Bertels, Vlad Mihai Sima, Yana Yankova, Georgi Kuzmanov, Wayne Luk, José Gabriel F. Coutinho, Fabrizio Ferrandi, Christian Pilato, Marco Lattuada, Donatella Sciuto, Andrea Michelotti. HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms
102 -- 104Shane Greenstein. Gatekeeping Economics