External Links

    Journal: IEEE Micro

    Volume 8, Issue 6

    13 -- 29Panos Papamichalis, Ray Simar Jr.. The TMS320C30 floating-point digital signal processor
    30 -- 48Michael L. Fuccio, Renato N. Gadenz, Craig J. Garen, Joan M. Huser, Benjamin Ng, Steven P. Pekarich, Kreg D. Ulery. The DSP32C: AT&Ts second generation floating point digital signal processor
    49 -- 67Guy R. L. Sohie, Kevin Kloker. A digital signal processor with IEEE floating-point arithmetic
    68 -- 85L. Robert Morris. A PC-based digital speech spectrograph

    Volume 8, Issue 5

    10 -- 29R. M. Lea. ASP: a cost-effective parallel microcomputer
    30 -- 46Jörg Kaiser. MUTABOR, a coprocessor supporting memory management in an object-oriented architecture
    47 -- 63Björn Bergsten, Rubén González-Rubio, Brigitte Kerhervé, Jean Rohmer. An advanced database accelerator
    64 -- 75David F. Hinnant. Accurate Unix benchmarking: art, science, or black magic?

    Volume 8, Issue 4

    6 -- 17Steven W. Yates, Ronald D. Williams. A fault-tolerant multiprocess controller for magnetic bearings
    18 -- 29Ronald D. Williams, Barry W. Johnson, Thomas E. Roberts. An operating system for a fault-tolerant multiprocessor controller
    30 -- 43Brenda M. Ozaki, Eduardo B. Fernández, Ehud Gudes. Software fault tolerance in architectures with hierarchical protection levels
    44 -- 54Donald B. Alpert, Michael J. Flynn. Performance trade-offs for microprocessor cache memories
    56 -- 61Elvira Argon, I-Lok Chang, Gamini Gunaratna, David K. Kahaner, Martin A. Reed. Mathematical software: Plod
    62 -- 75Tenkasi V. Ramabadran, Sunil S. Gaitonde. A tutorial on CRC computations

    Volume 8, Issue 3

    10 -- 26Clif Purkiser, Jim Kardach. The Intel 376 family for embedded processor applications
    28 -- 38Ron Cates. Processor architecture considerations for embedded controller applications
    39 -- 52Karl M. Guttag, Thomas M. Albers, Michael D. Asal, Kevin G. Rose. The TMS34010: an embedded microprocessor
    53 -- 62Chris Rowen, Mark Johnson, Paul Ries. The MIPS R3010 floating-point coprocessor
    63 -- 76David P. Ryan. Intel's 80960: an architecture optimized for embedded control
    77 -- 87Sorin Iacobovici. A pipelined interface for high floating-point performance with precise exceptions

    Volume 8, Issue 2

    12 -- 21Hideo Inayoshi, Ikuya Kawasaki, Tadahiko Nishimukai, Ken Sakamura. Realization of Gmicro/200
    22 -- 36Shinya Kimura, Yasuhiko Komoto, Yoichi Yano. Implementation of the V60/V70 and its FRM function
    37 -- 46Misao Miyata, Hidechika Kishigami, Kosei Okamoto, Shigeo Kamiya. The TX1 32-bit microprocessor: performance analysis, and debugging support
    47 -- 59Ken Sakamura, Royichi Sano, Kazuhiko Honma. Introducing Tobus: the system bus in the TRON architecture
    60 -- 66Ken Sakamura, Kanehisha Tsurumi, Hiro Kato. Applying the μBTRON bus to a music LAN
    67 -- 80Borivoje Furht. A RISC architecture with two-size, overlapping register windows

    Volume 8, Issue 1

    8 -- 27Jean-Daniel Nicoud. Video RAMs: structure and applications
    28 -- 56Harry Vlahos, Veljko Milutinovic. GaAs microprocessors and digital systems: an overview of R&D efforts
    57 -- 69Shreekant S. Thakkar, Paul Gifford, Gary N. Fielland. The Balance multiprocessor system
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