Journal: SIGARCH Computer Architecture News

Volume 18, Issue 4

10 -- 17Burton Smith. The end of architecture
18 -- 21Mark D. Hill. What is scalability?
22 -- 26Phillip A. Laplante. A novel single instruction computer architecture
27 -- 34Ran Ginosar, Nick Michell. On the potential of asynchronous pipelined processors
35 -- 52Yen-Jen Oyang, Chun-Hung Wen, Yu-Fen Chen, Shu-May Lin. The effect of employing advanced branching mechanisms in superscalar processors
52 -- 58Yannick Deville. A low-cost usage-based replacement algorithm for cache memories
59 -- 61Bernard K. Gunther. A high speed mechanism for short branches
62 -- 66Robert McLaughlin. Design for fast DSP machine
67 -- 77Werner B. Joerg. A subclass of Petri Nets as design abstraction for parallel architectures
80 -- 89Mark Thorson. Usenet Nuggets
90 -- 0Glen G. Langdon Jr.. Book review: Highly Parallel Computing by George Almasi and Allan Gotlieb (Benjamin/Cummings, 1989)
90 -- 91Glen G. Langdon Jr.. Book review: Solving Problems on Concurrent Processors, Vol II: Software for Concurrent Processors by I. Angus, G. Fox, J. Kim, and D. Walker (Prentice-Hall, 1990)
91 -- 0Marc Dikotter. Book review: The Definition of Standard ML by R. Milner, M. Torte, R. Harper

Volume 18, Issue 2

7 -- 14Wolfgang Matthes. Hardware Resources: a generalizing view on computer architectures
15 -- 24Lawrence Rauchwerger, P. Michael Farmwald. A multiple floating point coprocessor architecture
25 -- 32Andy Glew, Wen-mei Hwu. Snoopy cache test-and-test-and-set without execessive bus contention
33 -- 44Lee Higbee. Quick and easy cache performance analysis
45 -- 52Arvin Park, Jeffrey C. Becker, Richard J. Lipton. IOStone: a synthetic file system benchmark
53 -- 68Dionisios N. Pnevmatikatos, Mark D. Hill. Cache performance of the integer SPEC benchmarks on a RISC
69 -- 75Anthonie B. Ruighaver. A modular network for dense optical interconnection of processing elements
76 -- 84Alessandro De Gloria. VISA: A variable instruction set architecture
85 -- 89Fleur L. Williams, Gordon B. Steven. Address and data register separation on the M68000 family

Volume 18, Issue 1

9 -- 0V. Dvorak. Microseqencer architecture supporting arbitrary branching up to 2m targets
17 -- 0Jack J. Dongarra. Performance of various computers using standard linear equations software
32 -- 0Tsong-Chih Hsu, Ling-Yang Kung. A comment on "a fetch - and - op implementation for parallel computers"
35 -- 0Robert Cousins. A novel approach to character interfaces
43 -- 0Robert Cousins. A reentrant peripheral interface
51 -- 0Noel W. Anderson. Amorphous computer system architecture: a preliminary look
59 -- 0Yen-Jen Oyang, Bor-Ting Chang, Shu-May Lin. A cost-effective approach to implement a long instruction word microprrocessor
73 -- 0C. Fritsch, T. Sánchez, J. J. Anaya. Primitive based architectures
81 -- 0Harold Lorin. A model for recentralization of computing: (distributed processing comes home)
99 -- 0Dan Teodosiu 0002. Computing in three dimensions
107 -- 0Gary Frazier. Ariel: a scalable multiprocessor for the simulation of neural networks
120 -- 122Robert P. Colwell. Book review: High-Level Language Computer Architecture edited by Veljko Milutinovic (Computer Science Press, 1989)
122 -- 123Behrooz Parhami. Book review: Advanced Research in VLSI, edited by Charles L. Seitz (The MIT Press, Cambridge, MA, 1989, 373 pp.)