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    Journal: SIGARCH Computer Architecture News

    Volume 24, Issue 5

    1 -- 8Charlton D. Rose, J. Kelly Flanagan. Constructing instruction traces from cache-filtered address traces (CITCAT)
    9 -- 17Susan Flynn Hummel. Efficient data sharing with conditional remote memory transfers
    18 -- 22Larry Widigen, Elliot Sowadsky, Kevin McGrath. Eliminating operand read latency
    23 -- 30Philip Machanick. The case for SRAM main memory

    Volume 24, Issue 4

    3 -- 10Gerard Páez-Monzón, Charles Páez-Monzón. The RISC processor DMN-6: a unified data-control flow architecture
    11 -- 15J. A. Gómez Pulido, J. M. Sánchez Pérez, J. A. Moreno Zamora. An educational tool for testing hierarchical multilevel caches
    16 -- 0Samson Belayneh, David R. Kaeli. A discussion on non-blocking/lockup-free caches
    17 -- 18Mark Rosenbaum. Architectural potholes
    18 -- 0John Mashey. Architectural potholes
    18 -- 19Adrian Cockcroft. I/O potholes
    19 -- 20Zahir Ebrahim. I/O potholes
    20 -- 21Brad Carlile. Interpreting benchmarks
    21 -- 0David Chase. Register windows
    21 -- 22Paul W. DeMone. Register windows and delay slots

    Volume 24, Issue 3

    1 -- 8Jesús Carretero, Felix Pérez, Pedro de Miguel, Francisco García, L. Alonso. A massively parallel and distributed I/O subsystem
    9 -- 17Walter B. Ligon III, Daniel C. Stanzione Jr.. Distributing and load-balancing for loops in scientific applications
    18 -- 25Samson Belayneh, David R. Kaeli. A discussion on non-blocking/lockup-free caches
    26 -- 32Mark Thorson. Internet Nuggets

    Volume 24, Issue 1

    1 -- 5Trevor N. Mudge. Report on the panel: "how can computer architecture researchers avoid becoming the society for irreproducible results?"
    6 -- 11Oh-Young Kwon, Gi-Ho Park, Tack-Don Han. A compiler optimization to reduce execution time of loop nest
    12 -- 16Mark Thorson. Internet Nuggets
    17 -- 18Daniel Tabak. Book Review: Alpha Implementations and Architecture by Dileep P. Bhandarkar
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