| 7 | -- | 15 | Jack B. Dennis. Fresh Breeze: a multiprocessor chip architecture guided by modular programming principles |
| 16 | -- | 25 | David Morano, Alireza Khalafi, David R. Kaeli, Augustus K. Uht. Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture |
| 26 | -- | 38 | George Almási, Calin Cascaval, José G. Castaños, Monty Denneau, Derek Lieber, José E. Moreira, Henry S. Warren Jr.. Dissecting Cyclops: a detailed analysis of a multithreaded architecture |
| 39 | -- | 48 | Mohamed M. Zahran. On cache memory hierarchy for Chip-Multiprocessor |
| 49 | -- | 59 | Gary Gréwal, Tom Wilson, Andrew Morton. An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors |
| 60 | -- | 68 | Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer. 100 GOPS vision processor for automotive applications |
| 69 | -- | 74 | Nikos Pitsianis, Gerald G. Pechanek. Indirect VLIW memory allocation for the ManArray multiprocessor DSP |
| 75 | -- | 84 | Naohiko Shimizu, Ken Takatori. A transparent Linux super page kernel for Alpha, Sparc64 and IA32: reducing TLB misses of applications |
| 85 | -- | 92 | Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete. Fine-grain design space exploration for a cartographic SoC multiprocessor |
| 93 | -- | 96 | Mark Thorson. Internet nuggets |