Journal: SIGARCH Computer Architecture News

Volume 40, Issue 5

4 -- 9Kentaro Sano, Yoshiaki Kono. FPGA-based Connect6 solver with hardware-accelerated move refinement
10 -- 15Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung. Roberts: reconfigurable platform for benchmarking real-time systems
16 -- 21Kei Kinoshita, Daisuke Takano, Tomoyuki Okamura, Tetsuhiko Yao, Yoshiki Yamaguchi. An augmented reality system with a coarse-grained reconfigurable device
22 -- 27Nicholas Ng, Nobuko Yoshida, Xinyu Niu, Kuen Hung Tsoi. Session types: towards safe and fast reconfigurable programming
28 -- 33Rizwan Syed, Yajun Ha, Bharadwaj Veeravalli. A low overhead abstract architecture for FPGA resource management
34 -- 39Kuen Hung Tsoi, Tobias Becker, Wayne Luk. Modelling reconfigurable systems in event driven simulation
40 -- 45Zheng Zhi Shun, Tsutomu Maruyama. FPGA acceleration of CDO pricing based on correlation expansions
46 -- 51Hiroki Nakahara, Hiroyuki Nakanishi, Tsutomu Sasao. On a wideband fast fourier transform for a radio telescope
52 -- 57Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada. High performance phylogenetic analysis on CUDA-compatible GPUs
58 -- 63Colin Yu Lin, Hayden Kwok-Hay So. Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis
64 -- 69Jamshaid Sarwar Malik, Paolo Palazzari, Ahmed Hemani. Effort, resources, and abstraction vs performance in high-level synthesis: finding new answers to an old question
70 -- 75Takeshi Kakimoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri. Performance comparison of GPU programming frameworks with the striped Smith-Waterman algorithm
76 -- 81Julien Tribino, Antoine Trouvé, Hadrien A. Clarke, Kazuaki Murakami. PASTIS: a photonic arbitration with scalable token injection scheme
82 -- 86Takahiro Watanabe, Minoru Watanabe. 0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI
87 -- 92Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi. A non-volatile reconfigurable offloader for wireless sensor nodes
93 -- 112Mark Thorson. Internet nuggets

Volume 40, Issue 4

1 -- 2Marcos K. Aguilera, Dahlia Malkhi, Keith Marzullo, Alessandro Panconesi, Andrzej Pelc, Roger Wattenhofer. Announcing the 2012 Edsger W. Dijkstra prize in distributed computing
3 -- 9Subhashis Maitra, Amitabha Sinha. A new algorithm for computing triple-base number system
10 -- 25Shiv Kumar, Seshadri Krishna Murthy, G. Varaprasad, S. SivaSathya. Network load and traffic pattern on the capacity of wireless ad hoc networks
26 -- 31Mohd Nazrin Md. Isa, Khaled Benkrid, Thomas Clayton. Efficient architecture and scheduling technique for pairwise sequence alignment
32 -- 43Abdelkrim Kamel Oudjida, Nicolas Chaillet, Mohamed Lamine Berrandjia, Ahmed Liacha. r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers
44 -- 48Mark Thorson. Internet nuggets

Volume 40, Issue 2

1 -- 9Ben H. H. Juurlink, Cor Meenderinck. Amdahl's law for predicting the future of multicores considered harmful
10 -- 17Conrad Mueller. Axiom based architecture
18 -- 27Alexander Thomasian. Rebuild processing in RAID5 with emphasis on the supplementary parity augmentation method[37]
28 -- 32Nishant Kumar Giri, Amitabha Sinha. FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT
33 -- 38Aniruddha Ghosh, Satrughna Singha, Amitabha Sinha. A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system
39 -- 43Aniruddha Ghosh, Satrughna Singha, Amitabha Sinha. "Floating point RNS": a new concept for designing the MAC unit of digital signal processor
44 -- 49Mark Thorson. Internet nuggets