| 22 | -- | 0 | Michael R. Jantz, Prasad A. Kulkarni. 1 |
| 23 | -- | 0 | Xiangyu Dong, Norman P. Jouppi, Yuan Xie. A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies |
| 24 | -- | 0 | Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie. Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface |
| 25 | -- | 0 | Chien-Chi Chen, Sheng-De Wang. An efficient multicharacter transition string-matching engine based on the aho-corasick algorithm |
| 26 | -- | 0 | Yangchun Luo, Wei-Chung Hsu, Antonia Zhai. The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution |
| 27 | -- | 0 | Dyer Rolán, Basilio B. Fraguela, Ramon Doallo. 1 |
| 28 | -- | 0 | Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer. Using in-flight chains to build a scalable cache coherence protocol |
| 29 | -- | 0 | Daniel Sánchez, Yiannakis Sazeides, Juan M. Cebrian, José M. García 0001, Juan L. Aragón. Modeling the impact of permanent faults in caches |
| 30 | -- | 0 | Sanghoon Lee 0006, James Tuck. Automatic parallelization of fine-grained metafunctions on a chip multiprocessor |
| 31 | -- | 0 | Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla. Dynamic microarchitectural adaptation using machine learning |
| 32 | -- | 0 | Long Chen, Yanan Cao, Zhao Zhang. 3CC: A memory error protection scheme with novel address mapping for subranked and low-power memories |
| 33 | -- | 0 | Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez. Temporal-based multilevel correlating inclusive cache replacement |
| 34 | -- | 0 | Qixiao Liu, Miquel Moretó, Victor Jiménez, Jaume Abella, Francisco J. Cazorla, Mateo Valero. Hardware support for accurate per-task energy metering in multicore systems |
| 35 | -- | 0 | Sanyam Mehta, Gautham Beeraka, Pen-Chung Yew. Tile size selection revisited |
| 36 | -- | 0 | Bogdan Prisacari, Germán Rodríguez, Cyriel Minkenberg, Torsten Hoefler. Fast pattern-specific routing for fat tree networks |
| 37 | -- | 0 | Maximilien Breughe, Lieven Eeckhout. Selecting representative benchmark inputs for exploring microprocessor design spaces |
| 38 | -- | 0 | Christoph Kerschbaumer, Eric Hennigan, Per Larsen, Stefan Brunthaler, Michael Franz. Information flow tracking meets just-in-time compilation |
| 39 | -- | 0 | Rupesh Nasre. Time- and space-efficient flow-sensitive points-to analysis |
| 40 | -- | 0 | Wenjia Ruan, Yujie Liu, Michael F. Spear. Boosting timestamp-based transactional memory by exploiting hardware cycle counters |
| 41 | -- | 0 | Tanima Dey, Wei Wang, Jack W. Davidson, Mary Lou Soffa. ReSense: Mapping dynamic workloads of colocated multithreaded applications using resource sensitivity |
| 42 | -- | 0 | Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal. Techniques to improve performance in requester-wins hardware transactional memory |
| 43 | -- | 0 | Myeongjae Jeon, Conglong Li, Alan L. Cox, Scott Rixner. Reducing DRAM row activations with eager read/write clustering |
| 44 | -- | 0 | Zhijia Zhao, Michael Bebenita, Dave Herman, Jianhua Sun, Xipeng Shen. HPar: A practical parallel parser for HTML-taming HTML complexities for parallel parsing |
| 45 | -- | 0 | Ehsan Totoni, Mert Dikmen, María Jesús Garzarán. Easy, fast, and energy-efficient object detection on heterogeneous on-chip architectures |
| 46 | -- | 0 | Viacheslav V. Fedorov, Sheng Qiu, A. L. Narasimha Reddy, Paul V. Gratz. ARI: Adaptive LLC-memory traffic management |
| 47 | -- | 0 | Cecilia González-Alvarez, Jennifer B. Sartor, Carlos Alvarez, Daniel Jiménez-González, Lieven Eeckhout. Accelerating an application domain with specialized functional units |
| 48 | -- | 0 | Xiaolin Wang, Lingmei Weng, Zhenlin Wang, Yingwei Luo. Revisiting memory management on virtualized environments |
| 49 | -- | 0 | Chuntao Jiang, Zhibin Yu, Hai Jin, Cheng-Zhong Xu, Lieven Eeckhout, Wim Heirman, Trevor E. Carlson, Xiaofei Liao. PCantorSim: Accelerating parallel architecture simulation through fractal-based sampling |
| 50 | -- | 0 | Srdan Stipic, Vesna Smiljkovic, Osman S. Unsal, Adrián Cristal, Mateo Valero. Profile-guided transaction coalescing - lowering transactional overheads by merging transactions |
| 51 | -- | 0 | Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie 0001, Daniel A. Jiménez. WADE: Writeback-aware dynamic cache management for NVM-based main memory system |
| 52 | -- | 0 | Yong Li 0009, Yaojun Zhang, Hai Li, Yiran Chen, Alex K. Jones. C1C: A configurable, compiler-guided STT-RAM L1 cache |
| 53 | -- | 0 | Naznin Fauzia, Venmugil Elango, Mahesh Ravishankar, J. Ramanujam, Fabrice Rastello, Atanas Rountev, Louis-Noël Pouchet, P. Sadayappan. Beyond reuse distance analysis: Dynamic analysis for characterization of data locality potential |
| 54 | -- | 0 | Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors. Designing a practical data filter cache to improve both energy efficiency and performance |
| 55 | -- | 0 | Andrei Hagiescu, Bing Liu 0013, R. Ramanathan, Sucheendra K. Palaniappan, Zheng Cui, Bipasa Chattopadhyay, P. S. Thiagarajan, Weng-Fai Wong. GPU code generation for ODE-based applications with phased shared-data access patterns |
| 56 | -- | 0 | JungHee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Jongman Kim. TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era |
| 57 | -- | 0 | Christos Strydis, Robert M. Seepers, Pedro Peris-Lopez, Dimitrios Siskos, Ioannis Sourdis. A system architecture, processor, and communication protocol for secure implants |
| 58 | -- | 0 | Wonsub Kim, Yoonseo Choi, Haewoo Park. Fast modulo scheduler utilizing patternized routes for coarse-grained reconfigurable architectures |
| 59 | -- | 0 | Dorit Nuzman, Revital Eres, Sergei Dyshel, Marcel Zalmanovici, Jose Castanos. JIT technology with C/C++: Feedback-directed dynamic recompilation for statically compiled languages |
| 60 | -- | 0 | Thejas Ramashekar, Uday Bondhugula. Automatic data allocation and buffer management for multi-GPU machines |
| 61 | -- | 0 | Hans Vandierendonck, George Tzenakis, Dimitrios S. Nikolopoulos. Analysis of dependence tracking algorithms for task dataflow execution |
| 62 | -- | 0 | Yeonghun Jeong, Seongseok Seo, Jongeun Lee. Evaluator-executor transformation for efficient pipelining of loops with conditionals |
| 63 | -- | 0 | Rajkishore Barik, Jisheng Zhao, Vivek Sarkar. A decoupled non-SSA global register allocation using bipartite liveness graphs |
| 64 | -- | 0 | Peter Gavin, David B. Whalley, Magnus Själander. Reducing instruction fetch energy in multi-issue processors |