Journal: TACO

Volume 12, Issue 4

33 -- 0Subhasis Das, Tor M. Aamodt, William J. Dally. Reuse Distance-Based Probabilistic Cache Replacement
34 -- 0Etem Deniz, Alper Sen 0001. MINIME-GPU: Multicore Benchmark Synthesizer for GPUs
35 -- 0Li Tan, Zizhong Chen, Shuaiwen Leon Song. Scalable Energy Efficiency with Resilience for High Performance Computing Systems: A Quantitative Methodology
36 -- 0Kishore Kumar Pusukuri, Rajiv Gupta, Laxmi N. Bhuyan. Tumbler: An Effective Load-Balancing Technique for Multi-CPU Multicore Systems
37 -- 0Erik Tomusk, Christophe Dubach, Michael F. P. O'Boyle. Four Metrics to Evaluate Heterogeneous Multicores
38 -- 0Morteza Hoseinzadeh, Mohammad Arjomand, Hamid Sarbazi-Azad. SPCM: The Striped Phase Change Memory
39 -- 0Chuntao Jiang, Zhibin Yu, Lieven Eeckhout, Hai Jin, Xiaofei Liao, Cheng-Zhong Xu. Two-Level Hybrid Sampled Simulation of Multithreaded Applications
40 -- 0Sandeep D'Souza, Soumya J., Santanu Chattopadhyay. Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels
41 -- 0Dimitrios Chasapis, Marc Casas, Miquel Moretó, Raul Vidal, Eduard Ayguadé, Jesús Labarta, Mateo Valero. PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite
42 -- 0Francisco Gaspar, Luís Taniça, Pedro Tomás, Aleksandar Ilic, Leonel Sousa. A Framework for Application-Guided Task Management on Heterogeneous Embedded Systems
43 -- 0Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz, Jose Renau. Managing Mismatches in Voltage Stacking with CoreUnfolding
44 -- 0Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi. FaultSim: A Fast, Configurable Memory-Reliability Simulator for Conventional and 3D-Stacked Systems
45 -- 0Byeongcheol Lee. Adaptive Correction of Sampling Bias in Dynamic Call Graphs
46 -- 0Andrew J. McPherson, Vijay Nagarajan, Susmit Sarkar, Marcelo Cintra. Fence Placement for Legacy Data-Race-Free Programs via Synchronization Read Detection
47 -- 0Ding-Yong Hong, Chun-Chen Hsu, Cheng-Yi Chou, Wei-Chung Hsu, Pangfeng Liu, Jan-Jan Wu. Optimizing Control Transfer and Memory Virtualization in Full System Emulators
48 -- 0Aravind Sukumaran-Rajam, Philippe Clauss. The Polyhedral Model of Nonlinear Loops
49 -- 0Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi. Citadel: Efficiently Protecting Stacked Memory from TSV and Large Granularity Failures
50 -- 0Andrew Anderson, Avinash Malik, David Gregg. Automatic Vectorization of Interleaved Data Revisited
51 -- 0Lihang Zhao, Lizhong Chen, Woojin Choi, Jeffrey T. Draper. A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution
52 -- 0Olivier Serres, Abdullah Kayi, Ahmad Anbar, Tarek A. El-Ghazawi. Enabling PGAS Productivity with Hardware Support for Shared Address Mapping: A UPC Case Study
53 -- 0Riccardo Cattaneo, Giuseppe Natale, Carlo Sicignano, Donatella Sciuto, Marco Domenico Santambrogio. On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach
54 -- 0Unnikrishnan C., Rupesh Nasre, Y. N. Srikant. Falcon: A Graph Manipulation Language for Heterogeneous Systems
55 -- 0Rajshekar Kalayappan, Smruti R. Sarangi. FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Manycore Processors
56 -- 0Jesse Elwell, Ryan Riley, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Iliano Cervesato. Rethinking Memory Permissions for Protection Against Cross-Layer Attacks
57 -- 0Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar. Resistive GP-SIMD Processing-In-Memory
58 -- 0Yaohua Wang, Dong Wang, Shuming Chen, Zonglin Liu, Shenggang Chen, Xiaowen Chen, Xu Zhou. Iteration Interleaving-Based SIMD Lane Partition
59 -- 0Tomi Äijö, Pekka Jääskeläinen, Tapio Elomaa, Heikki Kultala, Jarmo Takala. Integer Linear Programming-Based Scheduling for Transport Triggered Architectures
60 -- 0Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero. Sensible Energy Accounting with Abstract Metering for Multicore Systems
61 -- 0Miao Zhou, Yu Du, Bruce R. Childers, Daniel Mossé, Rami G. Melhem. Symmetry-Agnostic Coordinated Management of the Memory Hierarchy in Multicore Systems
62 -- 0Amir Yazdanbakhsh, Gennady Pekhimenko, Bradley Thwaites, Hadi Esmaeilzadeh, Onur Mutlu, Todd C. Mowry. RFVP: Rollback-Free Value Prediction with Safe-to-Approximate Loads
63 -- 0Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Samira Manabi Khan, Onur Mutlu. Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost
64 -- 0Yeoul Na, Seon Wook Kim, Youngsun Han. JavaScript Parallelizing Compiler for Exploiting Parallelism from Data-Parallel HTML5 Applications
65 -- 0Hiroyuki Usui, Lavanya Subramanian, Kevin Kai-Wei Chang, Onur Mutlu. DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators
66 -- 0Morteza Mohajjel Kafshdooz, Mohammadkazem Taram, Sepehr Assadi, Alireza Ejlali. A Compile-Time Optimization Method for WCET Reduction in Real-Time Embedded Systems through Block Formation

Volume 12, Issue 3

26 -- 0Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras. The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence
27 -- 0Mark Gottscho, Abbas BanaiyanMofrad, Nikil D. Dutt, Alex Nicolau, Puneet Gupta. DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era
28 -- 0Pierre Michaud, Andrea Mondelli, André Seznec. Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters
29 -- 0Ragavendra Natarajan, Antonia Zhai. Leveraging Transactional Execution for Memory Consistency Model Emulation
30 -- 0Biswabandan Panda, Shankar Balachandran. CAFFEINE: A Utility-Driven Prefetcher Aggressiveness Engine for Multicores
31 -- 0Jishen Zhao, Sheng Li, Jichuan Chang, John L. Byrne, Laura L. Ramirez, Kevin T. Lim, Yuan Xie 0001, Paolo Faraboschi. Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion
32 -- 0Jan Lucas, Michael Andersch, Mauricio Alvarez Mesa, Ben H. H. Juurlink. Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency

Volume 12, Issue 2

9 -- 0Hamed Tabkhi, Gunar Schirner. A Joint SW/HW Approach for Reducing Register File Vulnerability
10 -- 0Arun K. Kanuparthi, Ramesh Karri. Reliable Integrity Checking in Multicore Processors
11 -- 0Do-Heon Lee, Su-Kyung Yoon, Jung-Geun Kim, Charles C. Weems, Shin-Dug Kim. A New Memory-Disk Integrated System with HW Optimizer
12 -- 0Morteza Mohajjel Kafshdooz, Alireza Ejlali. Dynamic Shared SPM Reuse for Real-Time Multicore Embedded Systems
13 -- 0Wenhao Jia, Elba Garza, Kelly A. Shaw, Margaret Martonosi. GPU Performance and Power Tuning Using Regression Trees
14 -- 0Irshad Pananilath, Aravind Acharya, Vinay Vasista, Uday Bondhugula. An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations
15 -- 0Shuangde Fang, Wenwen Xu, Yang Chen, Lieven Eeckhout, Olivier Temam, Yunji Chen, Chengyong Wu, Xiaobing Feng 0002. Practical Iterative Optimization for the Data Center
16 -- 0Tao Zhang, Naifeng Jing, Kaiming Jiang, Wei Shu, Min-You Wu, Xiaoyao Liang. Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs
17 -- 0Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie 0001. EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors
18 -- 0Arjun Suresh, Bharath Narasimha Swamy, Erven Rohou, André Seznec. Intercepting Functions for Memoization: A Case Study Using Transcendental Functions
19 -- 0Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang. SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs
20 -- 0Doug Simon, Christian Wimmer, Bernhard Urban, Gilles Duboscq, Lukas Stadler, Thomas Würthinger. Snippets: Taking the High Road to a Low Level
21 -- 0Raghuraman Balasubramanian, Vinay Gangadhar, Ziliang Guo, Chen-Han Ho, Cherin Joseph, Jaikrishnan Menon, Mario Paulo Drumond, Robin Paul, Sharath Prasad, Pradip Valathol, Karthikeyan Sankaralingam. Enabling GPGPU Low-Level Hardware Explorations with MIAOW: An Open-Source RTL Implementation of a GPGPU
22 -- 0Quan Chen, Minyi Guo. Locality-Aware Work Stealing Based on Online Profiling and Auto-Tuning for Multisocket Multicore Architectures
23 -- 0Madan Das, Gabriel Southern, Jose Renau. Section-Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication
24 -- 0Atieh Lotfi, Abbas Rahimi, Luca Benini, Rajesh K. Gupta. Aging-Aware Compilation for GP-GPUs
25 -- 0Brian P. Railing, Eric R. Hein, Thomas M. Conte. Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs

Volume 12, Issue 1

1 -- 0Christopher Zimmer, Frank Mueller. NoCMsg: A Scalable Message-Passing Abstraction for Network-on-Chips
2 -- 0Beayna Grigorian, Glenn Reinman. Accelerating Divergent Applications on SIMD Architectures Using Neural Networks
3 -- 0Anup Holey, Vineeth Mekkat, Pen-Chung Yew, Antonia Zhai. Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor
4 -- 0Jinho Suh, Chieh-Ting Huang, Michel Dubois. Dynamic MIPS Rate Stabilization for Complex Processors
5 -- 0Naghmeh Karimi, Arun Karthik Kanuparthi, Xueyang Wang, Ozgur Sinanoglu, Ramesh Karri. MAGIC: Malicious Aging in Circuits/Cores
6 -- 0Pablo de Oliveira Castro, Chadi Akel, Eric Petit, Mihail Popov, William Jalby. CERE: LLVM-Based Codelet Extractor and REplayer for Piecewise Benchmarking and Optimization
7 -- 0Benedict R. Gaster, Derek Hower, Lee W. Howes. HRF-Relaxed: Adapting HRF to the Complexities of Industrial Heterogeneous Memory Models
8 -- 0Kevin Streit, Johannes Doerfert, Clemens Hammacher, Andreas Zeller, Sebastian Hack. Generalized Task Parallelism