359 | -- | 389 | Jedidiah R. Crandall, Shyhtsun Felix Wu, Frederic T. Chong. Minos: Architectural support for protecting control data |
390 | -- | 423 | Jaydeep Marathe, Frank Mueller, Bronis R. de Supinski. Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques |
424 | -- | 449 | Ilya Ganusov, Martin Burtscher. Future execution: A prefetching mechanism that uses multiple cores to speed up single threads |
450 | -- | 476 | Michele Co, Dee A. B. Weikle, Kevin Skadron. Evaluating trace cache energy efficiency |
477 | -- | 501 | Shiwen Hu, Madhavi Gopal Valluri, Lizy Kurian John. Effective management of multiple configurable units using dynamic optimization |
502 | -- | 527 | Chris Bentley, Scott A. Watterson, David K. Lowenthal, Barry Rountree. Implicit array bounds checking on 64-bit architectures |