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Journal: IEEE Transactions on Computers

Volume 24, Issue 3

226 -- 232Peter G. Neumann, T. R. N. Rao. Error-Correcting Codes for Byte-Organized Arithmetic Processors
233 -- 242Stephen S. Yau, Shih-Chien Yang. Multiple Fault Detection for Combinational Logic Circuits
242 -- 249Oscar H. Ibarra, Sartaj Sahni. Polynomially Complete Fault Detection Problems
250 -- 258Mohamed I. Elmasry, Philip M. Thompson. Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers
258 -- 280Angelo Raffaele Meo. Arithmetic Networks and Their Minimization Using a New Line of Elementary Units
281 -- 289Donald H. Foley, John W. Sammon Jr.. An Optimal Set of Discriminant Vectors
290 -- 298Charles S. Weaver. Some Properties of Threshold Logic Unit Pattern Recognition Networks
299 -- 304Johannes Mykkeltveit. Generating and Counting the Double Adjacencies in a Pure Circulating Shift Register
305 -- 310Michal Servít. Hazard Correction in Synchronous Sequential Circuits
310 -- 313Gian Carlo Bongiovanni, Fabrizio Luccio, Alessandro Zorat. The Discrete Equation of the Straight Line
313 -- 317C. K. Yuen. Computing Robust Walsh-Fourier Transform by Error Product Minimization
317 -- 322John Deverell. Pipeline Iterative Arithmetic Arrays
322 -- 325P. W. Baker. Parallel Multiplicative Algorithms for Some Elementary Functions
325 -- 329C. K. Yuen. A Note on Base -2 Arithmetic Logic
329 -- 331Russel J. Niederjohn, Philip P. Stick. A Computer Interface for Efficient Zero-Crossing Interval Measurement
331 -- 335John P. Robinson, Charles W. Hoffner II. Easily Tested Three-Level Gate Networks for ::::T:::: or More of ::::N:::: Symmetric Functions
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