| 1121 | -- | 1128 | Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin. Area Time Trade-Offs in Micro-Grain VLSI Array Architectures |
| 1129 | -- | 1139 | . Memory Latency Effects in Decoupled Architectures |
| 1140 | -- | 1150 | Gideon D. Intrater, Ilan Y. Spillinger. Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers |
| 1151 | -- | 1162 | Kang G. Shin, Hagbae Kim. A Time Redundancy Approach to TMR Failures Using Fault-State Likelihoods |
| 1163 | -- | 1174 | Dhiraj K. Pradhan, Nitin H. Vaidya. Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture |
| 1175 | -- | 1183 | Michael Harrington, Arun K. Somani. Synchronizing Hypercube Networks in the Presence of Faults |
| 1184 | -- | 1196 | Sameer M. Bataineh, Te-Yu Hsiung, Thomas G. Robertazzi. Closed Form Solutions for Bus and Tree Networks of Processors Load Sharing a Divisible Job |
| 1197 | -- | 1209 | Jordan Gergov, Christoph Meinel. Efficient Boolean Manipulation With OBDD s can be Extended to FBDD s |
| 1210 | -- | 1220 | Jehoshua Bruck, Robert Cypher, Danny Soroker. Embedding Cube-Connected Cycles Graphs into Faulty Hypercubes |
| 1221 | -- | 1226 | Dwijendra K. Ray-Chaudhuri, N. M. Singhi, S. Sanyal, P. S. Subramanian. Theory and Design of t-Unidirectional Error-Correcting and d-Unidirectional Error-Detecting Code |
| 1226 | -- | 1232 | R. F. Tinder, R. I. Klaus, J. A. Snodderley. High-Speed Microprogrammable Asynchronous Controller Modules |
| 1232 | -- | 1237 | Daniel Pak-Kong Lun, Wan-Chi Siu. A Pipeline Design for the Realization of the Prime Factor Algorithm Using the Extended Diagonal Structure |
| 1238 | -- | 1240 | J. Q. Wang, Parag K. Lala. Partially Strongly Fault Secure and Partially Strongly Code Disjoint I-out-of-3 Code Checker |
| 1240 | -- | 1247 | Rajib K. Das, Krishnendu Mukhopadhyaya, Bhabani P. Sinha. A New Family of Bridged and Twisted Hypercubes |