Journal: IEEE Trans. on Circuits and Systems

Volume 63, Issue 5

565 -- 566Mario di Bernardo, Eduardo Antonio Barros da Silva, Philipp Häfliger, Gianluca Setti. Guest Editorial Special Section on the 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015)
567 -- 576Paul P. Sotiriadis. Spurs-Free Single-Bit-Output All-Digital Frequency Synthesizers With Forward and Feedback Spurs and Noise Cancellation
577 -- 586Georges G. E. Gielen, Jelle Van Rethy, Jorge Marin, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra. Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies
587 -- 598Lucian-Vasile Stoica, Valentyn Solomko, Thorsten Baumheinrich, Renato Del Regno, Reece Beigh, Geoff Rickard, Paul Williams, Steve Riches. A High Temperature Frequency Signal Conditioning Unit for Aeronautical Rotating Systems
599 -- 608Jie Zhang, Kerron Duncan, Yuanming Suo, Tao Xiong, Srinjoy Mitra, Trac Duy Tran, Ralph Etienne-Cummings. Communication Channel Analysis and Real Time Compressed Sensing for High Density Neural Recording Devices
609 -- 616Vanessa Senger, Ronald Tetzlaff. New Signal Processing Methods for the Development of Seizure Warning Devices in Epilepsy
617 -- 628Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Boxun Li, Yu Wang, Hao Jiang, Mark Barnell, Qing Wu, Jianhua Yang, Hai Li, Yiran Chen. Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators
629 -- 638Yue Zhang, Chao Zhang, Jiang Nan, Zhizhong Zhang, Xueying Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao. Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System
639 -- 649Gabriel A. Rincón-Mora, Siyu Yang. Tiny Piezoelectric Harvesters: Principles, Constraints, and Power Conversion
650 -- 660Daniel K. Molzahn, Ian A. Hiskens. Convex Relaxations of Optimal Power Flow Problems: An Illustrative Example
661 -- 670Tao Wang, Hsiao-Dong Chiang. On the Number of System Separations in Electric Power Systems
671 -- 682Xun Liu, Philip K. T. Mok, Junmin Jiang, Wing-Hung Ki. Analysis and Design Considerations of Integrated 3-Level Buck Converters
683 -- 692Tsung-Han Tsai, Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, Hsin-Shu Chen. An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique
693 -- 704Yingyan Lin, Min-Sun Keel, Adam C. Faust, Aolin Xu, Naresh R. Shanbhag, Elyse Rosenbaum, Andrew C. Singer. A Study of BER-Optimal ADC-Based Receiver for Serial Links
705 -- 715Jerry Lemberg, Marko Kosunen, Enrico Roverato, Mikko Martelius, Kari Stadius, Lauri Anttila, Mikko Valkama, Jussi Ryynänen. Digital Interpolating Phase Modulator for Wideband Outphasing Transmitters
716 -- 726Abisai Ramirez-Perez, Ramón Parra-Michel, Alberto Rodriguez-Garcia, Luis F. Gonzalez-Perez. A New Single h and Multi-h CPM Transmitter
727 -- 738Nai-Chung Kuo, Bo Zhao, Ali M. Niknejad. Bifurcation Analysis in Weakly-Coupled Inductive Power Transfer Systems

Volume 63, Issue 4

449 -- 458Yan Song, Zhongming Xue, Yi Xie, Shiquan Fan, Li Geng. A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications
459 -- 469Timothy A. Monk, Paul J. Hurst, Stephen H. Lewis. Iterative Gain Enhancement in an Algorithmic ADC
470 -- 481Pablo Castro-Lisboa, Pablo Perez-Nicoli, Francisco Veirano, Fernando Silveira. General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters
482 -- 493Kyongsu Lee, Jae-Yoon Sim. A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling
494 -- 502Radit Smunyahirun, Eng Leong Tan. Derivation of the Most Energy-Efficient Source Functions by Using Calculus of Variations
503 -- 516Xifan Tang, Gain Kim, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. A Study on the Programming Structures for RRAM-Based FPGA Architectures
517 -- 528Ju-Hong Lee, Jiun-Shian Du. The Phase Characteristics for the Stability of 2-D Nonsymmetric Half-Plane Digital Allpass Filters
529 -- 539Seyed Amir Reza Ahmadi Mehr, Massoud Tohidian, Robert Bogdan Staszewski. Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise
540 -- 550Ikchan Jang, Yoonmyung Lee, Soyoung Kim, Jintae Kim. Power-Performance Tradeoff Analysis of CML-Based High-Speed Transmitter Designs Using Circuit-Level Optimization
551 -- 560Jun Yang, Bin Wu, Shihua Li, Xinghuo Yu. Design and Qualitative Robustness Analysis of an DOBC Approach for DC-DC Buck Converters With Unmatched Circuit Parameter Perturbations

Volume 63, Issue 3

337 -- 346Shao Yong Zheng, Zhao Wu Liu, Yong Mei Pan, Yongle Wu, Wing Shing Chan, Yuanan Liu. Bandpass Filtering Doherty Power Amplifier With Enhanced Efficiency and Wideband Harmonic Suppression
347 -- 358Ehsan Ali, Christian Hangmann, Christian Hedayat, Fayrouz Haddad, Wenceslas Rahajandraibe, Ulrich Hilleringmann. Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL
359 -- 369Youchang Kim, Injoon Hong, Junyoung Park, Hoi-Jun Yoo. A 0.5 V 54 µW Ultra-Low-Power Object Matching Processor for Micro Air Vehicle Navigation
370 -- 378Jongwook Sohn, Earl E. Swartzlander Jr.. A Fused Floating-Point Four-Term Dot Product Unit
379 -- 388Paolo Maffezzoni, Bichoy Bahr, Zheng Zhang, Luca Daniel. Reducing Phase Noise in Multi-Phase Oscillators
389 -- 400Alon Ascoli, Ronald Tetzlaff, Leon O. Chua, John Paul Strachan, Richard Stanley Williams. History Erase Effect in a Non-Volatile Memristor
401 -- 412Qianxue Wang, Simin Yu, Chengqing Li, Jinhu Lu, Xiaole Fang, Christophe Guyeux, Jacques M. Bahi. Theoretical Design and FPGA-Based Implementation of Higher-Dimensional Digital Chaotic Systems
413 -- 422Alberto Oliveri, Flavio Stellino, Guido Caluori, Mauro Parodi, Marco Storace. Open-Loop Compensation of Hysteresis and Creep Through a Power-Law Circuit Model
423 -- 435Bo Zhou, Patrick Chiang. Short-Range Low-Data-Rate FM-UWB Transceivers: Overview, Analysis, and Design
436 -- 447Onur Dizdar, Erdal Arikan. A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic