| 151 | -- | 163 | Chien-Yu Chen, Zhong-Lan Yang, Tu-Chih Wang, Liang-Gee Chen. A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform |
| 165 | -- | 185 | Marco Ferretti, Davide Rizzo. A Parallel Architecture for the 2-D Discrete Wavelet Transform with Integer Lifting Scheme |
| 187 | -- | 203 | José Fridman, Elias S. Manolakos. Distributed Memory Parallel Architecture Based on Modular Linear Arrays for 2-D Separable Transforms Computation |
| 205 | -- | 220 | Shen-Fu Hsiao, Jian-Ming Tseng. Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec |
| 221 | -- | 234 | Edwin A. Hakkennes, Stamatis Vassiliadis. Multimedia Execution Hardware Accelerator |
| 235 | -- | 243 | Ding-Ming Kwai, Behrooz Parhami. Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization |
| 245 | -- | 257 | Gregory Doumenis, George E. Konstantoulakis, G. Korinthios, George Lykakis, Dionisios I. Reisis, G. Synnefakis. A Parallel VLSI Video/Communication Controller |
| 259 | -- | 278 | Francesco Gregoretti, Roberto Passerone, Leonardo Maria Reyneri, Claudio Sansoè. A High Speed VLSI Architecture for Handwriting Recognition |