Journal: VLSI Signal Processing

Volume 69, Issue 2

115 -- 123Zhen-dong Zhang, Bin Wu, Yong-xu Zhu, Yu-mei Zhou. An Area-Efficient 4-Stream FIR Interpolation/Decimation for IEEE 802.11n WLAN
125 -- 132Noureddine Boulejfen, F. M. Elsayed, Mohamed Helaoui, L. DeVocht, Fadhel M. Ghannouchi. Efficiency Enhancement of Sigma-Delta Modulator Based Transmitters Using Multi-Level Quantizers
133 -- 142Saif alZahir, Arber Borici. An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data
143 -- 159Amine Samet, A. Hachicha, Mohamed Ali Ben Ayed, Nouri Masmoudi. Implementation and Optimization of an Enhanced PWD Metric for H.264/AVC on a TMS320C64 DSP
161 -- 171Waqar Hussain, Fabio Garzia, Tapani Ahonen, Jari Nurmi. Designing Fast Fourier Transform Accelerators for Orthogonal Frequency-Division Multiplexing Systems
173 -- 188Tiantian Liu, Minming Li, Chun Jason Xue. Instruction Cache Locking for Embedded Systems using Probability Profile
189 -- 196Mohammad Torabi, Abbas Vafaei. A Fast Architecture for H.264/AVC Deblocking Filter Using a Clock Cycles Saving Process
197 -- 211Chiou-Yng Lee, Che Wun Chiou. Scalable Gaussian Normal Basis Multipliers over GF(2 m ) Using Hankel Matrix-Vector Representation
213 -- 224Nandini Ramesh Kumar, Wei Xiang, Yafeng Wang. Two-Symbol FPGA Architecture for Fast Arithmetic Encoding in JPEG 2000