Journal: VLSI Signal Processing

Volume 40, Issue 3

279 -- 280Myung Hoon Sunwoo, Wonyong Sung. Guest Editorial
281 -- 287Jung L. Lee, Myung Hoon Sunwoo. Implementation of a Wireless Multimedia DSP Chip for Mobile Applications
289 -- 299Dong-Ik Ko, Shuvra S. Bhattacharyya. Modeling of Block-Based DSP Systems
301 -- 310Wonyong Sung, Youngho Ahn, Eunjoo Hwang. VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers
311 -- 333Finbarr O Regan, Conor Heneghan. A Low Power Algorithm for Sparse System Identification using Cross-Correlation
335 -- 342Mehboob Alam, Wael M. Badawy, Vassil S. Dimitrov, Graham A. Jullien. An Efficient Architecture for a Lifted 2D Biorthogonal DWT
343 -- 353Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen. VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization
355 -- 369Tarek Darwish, Magdy Bayoumi. Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures
371 -- 382Mohammad M. Mansour, Naresh R. Shanbhag. A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes
383 -- 396Marc Leeman, David Atienza, Geert Deconinck, Vincenzo De Florio, José M. Mendías, Chantal Ykman-Couvreur, Francky Catthoor, Rudy Lauwereins. Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications

Volume 40, Issue 2

159 -- 174Fan Xu, Guichang Zhong, Alan N. Willson Jr.. Analysis and VLSI Realization of a Blind Beamforming Algorithm
175 -- 188Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen. VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters
189 -- 213Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés. FPGA Implementation of a Pipelined On-Line Backpropagation
215 -- 237Jarno K. Tanskanen, Reiner Creutzburg, Jarkko Niittylahti. On Design of Parallel Memory Access Schemes for Video Coding
239 -- 259Sangjin Hong, Shu-Shin Chin. Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications
261 -- 271Albert Mo Kim Cheng, Rajat Agarwal. Reducing Encoder Bit-Rate Variation in MPEG Video

Volume 40, Issue 1

5 -- 6Michael J. Schulte, Shuvra S. Bhattacharyya, Robert Schreiber. Guest Editorial
7 -- 18Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere. Solving Out-of-Order Communication in Kahn Process Networks
19 -- 34Holger Blume, H. T. Feldkämper, Tobias G. Noll. Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
35 -- 55Alain Darte, Guillaume Huard. New Complexity Results on Array Contraction and Related Problems
57 -- 72Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy, Abhijit Mahajan. VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance
73 -- 84Jeffrey T. Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca. A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System
85 -- 108Ruby B. Lee, A. Murat Fiskiran. PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing
109 -- 123José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera. High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation
125 -- 141Neil Burgess. New Models of Prefix Adder Topologies
143 -- 152Peter Kornerup. Reviewing 4-to-2 Adders for Multi-Operand Addition