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    Journal: VLSI Signal Processing

    Volume 50, Issue 3

    267 -- 280Li Teng, Laiwan Chan. Discovering Biclusters by Iteratively Sorting with Weighted Correlation Coefficient in Gene Expression Data
    281 -- 292Benson S. Y. Lam, Alan Wee-Chung Liew, David Keith Smith, Hong Yan. A Regularized Clustering Algorithm Based on Calculus of Variations
    293 -- 304Zhaohui Gan, Tommy W. S. Chow, D. Huang. Effective Gene Selection Method Using Bayesian Discriminant Based Criterion and Genetic Algorithms
    305 -- 320Yu-Ping Wang, Maheswar Gunampally, Jie Chen, Douglas Bittel, Merlin G. Butler, Wei-Wen Cai. A Comparison of Fuzzy Clustering Approaches for Quantification of Microarray Gene Expression
    321 -- 329Robin Kramer, Dong Xu. Projecting Gene Expression Trajectories through Inducing Differential Equations from Microarray Time Series Experiments
    331 -- 340Sujimarn Suwannaroj, Mahesan Niranjan. Enhancing Automatic Construction of Gene Subnetworks by Integrating Multiple Sources of Information

    Volume 50, Issue 2

    97 -- 98Shuvra S. Bhattacharyya, Jarmo Takala, Georgi Gaydadjiev. Introduction to the Special Issue on Embedded Computing Systems for DSP
    99 -- 114Andy D. Pimentel, Mark Thompson, Simon Polstra, Cagkan Erbas. Calibration of Abstract Performance Models for System-Level Design Space Exploration
    115 -- 136Ye Wen, Selim Gurun, Navraj Chohan, Richard Wolski, Chandra Krintz. Accurate and Scalable Simulation of Network of Heterogeneous Sensor Devices
    137 -- 161Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal. Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications
    163 -- 177Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya. Memory-constrained Block Processing for DSP Software Optimization
    179 -- 200Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis. Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path
    201 -- 229Mladen Berekovic, Tim Niggemeier. A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance
    231 -- 249Eero Aho, Jarno Vanne, Timo D. Hämäläinen. Configurable Data Memory for Multimedia Processing
    251 -- 261Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl. Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box

    Volume 50, Issue 1

    1 -- 17Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Liang-Gee Chen. Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
    19 -- 32Yu Li, Yun He, Shunliang Mei. A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC
    33 -- 39Jonah Probell. Architecture Considerations for Multi-Format Programmable Video Processors
    41 -- 51Yanmei Qu, Yun He, Shunliang Mei. A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC
    53 -- 67Sung Dae Kim, Myung Hoon Sunwoo. ASIP Approach for Implementation of H.264/AVC
    69 -- 80Tsu-Ming Liu, Chen-Yi Lee. Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead
    81 -- 95Lingfeng Li, Yang Song, Shen Li, Takeshi Ikenaga, Satoshi Goto. A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC
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