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A VLSI Circuit Model Accounting for Wire Delay

Ce Jin 0001, R. Ryan Williams, Nathaniel Young. A VLSI Circuit Model Accounting for Wire Delay. In Venkatesan Guruswami, editor, 15th Innovations in Theoretical Computer Science Conference, ITCS 2024, January 30 to February 2, 2024, Berkeley, CA, USA. Volume 287 of LIPIcs, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2024. [doi]

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