Algorithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC

Yun Chen 0001, Qiang Zhang, Yunlong Ge, YuanZhou Hu, Jie Chen, Na Ding, Xiaoyang Zeng, Defeng Huang. Algorithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC. In IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013. pages 932-935, IEEE, 2013. [doi]

@inproceedings{0001ZGHCDZH13,
  title = {Algorithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC},
  author = {Yun Chen 0001 and Qiang Zhang and Yunlong Ge and YuanZhou Hu and Jie Chen and Na Ding and Xiaoyang Zeng and Defeng Huang},
  year = {2013},
  doi = {10.1109/MWSCAS.2013.6674803},
  url = {https://doi.org/10.1109/MWSCAS.2013.6674803},
  researchr = {https://researchr.org/publication/0001ZGHCDZH13},
  cites = {0},
  citedby = {0},
  pages = {932-935},
  booktitle = {IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013},
  publisher = {IEEE},
}