Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow - researchr publication authors

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Mohamed Abbas, Makoto Ikeda, Kunihiro Asada. Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. In Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubatova, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jiri Bucek, editors, Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006. pages 147-148, IEEE Computer Society, 2006.

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